-
公开(公告)号：US20220020816A1
公开(公告)日：2022-01-20
申请号：US17489425
申请日：2021-09-29
Inventor： Philippe BOIVIN , Jean Jacques FAGOT , Emmanuel PETITPREZ , Emeline SOUCHIER , Olivier WEBER
Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.
-
公开(公告)号：US20200381617A1
公开(公告)日：2020-12-03
申请号：US16879577
申请日：2020-05-20
Inventor： Philippe BOIVIN , Daniel BENOIT , Remy BERTHELON
Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.
-
公开(公告)号：US20190259942A1
公开(公告)日：2019-08-22
申请号：US16400649
申请日：2019-05-01
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Philippe BOIVIN
Abstract: A oxide-based direct-access resistive nonvolatile memory may include within the interconnect portion of the integrated circuit a memory plane including capacitive memory cells extending in orthogonal first and second directions and each including a first electrode, a dielectric region and a second electrode. The memory plane may include conductive pads of square or rectangular shape forming the first electrodes. The stack of the dielectric layer and the second conductive layer covers the pads in the first direction and forms, in the second direction, conductive bands extending over and between the pads. The second electrodes may be formed by zones of the second bands facing the pads.
-
公开(公告)号：US20190057981A1
公开(公告)日：2019-02-21
申请号：US16057466
申请日：2018-08-07
Inventor： Jean-Jacques FAGOT , Philippe BOIVIN , Franck ARNAUD
Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
-
公开(公告)号：US20180330780A1
公开(公告)日：2018-11-15
申请号：US15978003
申请日：2018-05-11
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Philippe BOIVIN , Simon JEANNOT , Olivier WEBER
Abstract: The disclosure relates to a memory cell comprising a resistive RAM memory element and a selection transistor, in which the memory element is positioned on a flank of the selection transistor.
-
Patent Agency Ranking
公开(公告)号：US20240407179A1
公开(公告)日：2024-12-05
申请号：US18807821
申请日：2024-08-16
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Philippe BOIVIN
Abstract: The disclosure concerns a resistive memory cell, including a stack of a selector, of a resistive element, and of a layer of phase-change material, the selector having no physical contact with the phase-change material. In one embodiment, the selector is an ovonic threshold switch formed on a conductive track of a metallization level.
-
17.发明公开公开(公告)号：US20230260574A1
公开(公告)日：2023-08-17
申请号：US17673550
申请日：2022-02-16
Applicant: Universite D'Aix Marseille , Centre National De La Recherche Scientifique , STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Jean-Michel PORTAL , Vincenzo DELLA MARCA , Jean-Pierre WALDER , Julien GASQUEZ , Philippe BOIVIN
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C2213/72 , G11C2013/0054
Abstract: Memory devices such as phase change memory (PCM) devices utilizing Ovonic Threshold Switching (OTS) selectors may be used to fill the gap between dynamic random-access memory (DRAM) and mass storage and may be incorporated in high-end microcontrollers. Since the programming efficiency and reading phase efficiency of such devices is directly linked to the leakage current of the OTS selector as well as sneak-path management, a sense amplifier disclosed herein generates an auto-reference that takes into account the leakage currents of unselected cells and includes a regulation loop to compensate for voltage drop due to read current sensing. This auto-referenced sense amplifier, built utilizing the principle of charge-sharing, may be designed on a 28 nm fully depleted silicon-on-insulator (FDSOI) technology, provides robust performance for a wide range of sneak-path currents and consequently for a large range of memory array sizes, and is therefore suitable for use in embedded memory in high-end microcontroller.
-
公开(公告)号：US20220336736A1
公开(公告)日：2022-10-20
申请号：US17856711
申请日：2022-07-01
Inventor： Philippe BOIVIN , Daniel BENOIT , Remy BERTHELON
Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.
-
公开(公告)号：US20220123119A1
公开(公告)日：2022-04-21
申请号：US17504198
申请日：2021-10-18
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Christian RIVERO , Philippe BOIVIN , Francois TAILLIET , Roberto SIMOLA
IPC: H01L29/423 , H01L27/11524 , H01L29/788 , H01L21/28 , H01L29/66
Abstract: A memory transistor for a non-volatile memory cell includes a source region and a drain region implanted in a semiconductor substrate. The source region is spaced from the drain region. A double gate region for the memory transistor extends at least partly in depth in the semiconductor substrate between the source region and the drain region and further extends beyond this source region and this drain region. The memory cell further includes a selection transistor having a gate region that partially extends over the double gate region for the memory transistor.
-
公开(公告)号：US20140127873A1
公开(公告)日：2014-05-08
申请号：US14074059
申请日：2013-11-07
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Philippe BOIVIN
IPC: H01L29/66
CPC classification number: H01L29/66833 , H01L21/28273 , H01L21/28282 , H01L21/283 , H01L21/768 , H01L27/1052 , H01L27/11206 , H01L27/11521 , H01L27/11524 , H01L27/11563 , H01L27/11568 , H01L27/1157 , H01L29/42328 , H01L29/42344 , H01L29/66825 , H01L29/7881 , H01L29/792
Abstract: A method for fabricating at least one cell of a semiconducting component includes positioning a first conducting polysilicon-type layer on a substrate, above an insulating oxide-type layer. The production of at least one trench within the first conducting layer is included to form two electrically unlinked distinct conducting parts intended to form two transistor gates of respectively two distinct twin cells.
Abstract translation: 一种用于制造半导体元件的至少一个元件的方法包括将第一导电多晶硅型层定位在绝缘氧化物层上方的衬底上。 包括在第一导电层内产生至少一个沟槽以形成两个电气不连接的不同的导电部件，用于形成分别为两个不同的双电池的两个晶体管栅极。
-
-
-
-
-
-
-
-
-
Search Results
32
records
(took 0.013 seconds)
