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    Adaptive delay based asynchronous successive approximation analog-to-digital converter
    11.
    发明授权
    Adaptive delay based asynchronous successive approximation analog-to-digital converter 有权
    基于自适应延迟的异步逐次逼近模数转换器

    公开(公告)号：US09258008B2

    公开(公告)日：2016-02-09

    申请号：US14230370

    申请日：2014-03-31

    Applicant: STMicroelectronics International N.V.

    Inventor： Pratap Narayan Singh ,  Ashish Sharma Kumar ,  Chandrajit Debnath ,  Rakesh Malik

    IPC: H03M1/00 ,  H03M1/46 ,  H03M1/12 ,  H03M1/06

    CPC classification number: H03M1/125 ,  H03M1/00 ,  H03M1/0612 ,  H03M1/069 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/46 ,  H03M1/462

    Abstract: An asynchronous SAR ADC to convert an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.

    Abstract translation: 异步SAR ADC，以高效，低功耗的方式将模拟信号转换为一系列数字脉冲。 在同步SAR ADC电路中，单独和繁琐的时钟信号用于触发SAR ADC的内部电路。 异步解决方案不是以时钟信号同步触发SAR DAC的组件，而是以其自身的内部信号以异步循环方式触发其组件。 此外，为了提高效率并防止由于瞬态信号引起的困难而导致的电路故障，异步SAR ADC还可以包括用于将可变延迟引入SAR ADC周期的延迟电路。

    ADAPTIVE DELAY BASED ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER
    15.
    发明申请
    ADAPTIVE DELAY BASED ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER 审中-公开
    基于自适应延迟的异步连续逼近模拟数字转换器

    公开(公告)号：US20160056830A1

    公开(公告)日：2016-02-25

    申请号：US14930708

    申请日：2015-11-03

    Applicant: STMicroelectronics International N.V.

    Inventor： Rakesh Malik ,  Chandrajit Debnath ,  Ashish Sharma Kumar ,  Pratap Narayan Singh

    IPC: H03M1/12 ,  H03M1/46 ,  H03M1/06

    CPC classification number: H03M1/125 ,  H03M1/00 ,  H03M1/0612 ,  H03M1/069 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/46 ,  H03M1/462

    Abstract: An asynchronous SAR ADC converts an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.

    Abstract translation: 异步SAR ADC以有效，低功耗的方式将模拟信号转换为一系列数字脉冲。 在同步SAR ADC电路中，单独和繁琐的时钟信号用于触发SAR ADC的内部电路。 异步解决方案不是以时钟信号同步触发SAR DAC的组件，而是以其自身的内部信号以异步循环方式触发其组件。 此外，为了提高效率并防止由于瞬态信号引起的困难而导致的电路故障，异步SAR ADC还可以包括用于将可变延迟引入SAR ADC周期的延迟电路。

    Level shifting circuit with adaptive feedback
    16.
    发明授权
    Level shifting circuit with adaptive feedback 有权
    具有自适应反馈的电平移位电路

    公开(公告)号：US09000826B2

    公开(公告)日：2015-04-07

    申请号：US14280807

    申请日：2014-05-19

    Applicant: STMicroelectronics International N.V.

    Inventor： Adeel Ahmad ,  Chandrajit Debnath

    IPC: H03L5/00 ,  H03F3/45 ,  H03K19/0185

    CPC classification number: H03L5/00 ,  H03F3/45179 ,  H03K19/018528

    Abstract: An amplifier has a first pull-up path coupled between a voltage supply node and an output node, and a pull-down path coupled between the output node and a ground supply node. A second pull-up path is coupled between the voltage supply node and the output node. The second pull-up path is actuated by a feedback signal and biased by a biasing signal. An inverter circuit is operable to invert the signal at the amplifier output node to generate the feedback signal. A biasing circuit is configured to generate the biasing signal. The biasing circuit is configured to control a relative strength of the pull-down path to the second pull-up path, wherein the pull-down path is stronger than the second pull-up path in a manner that is consistently present over all PVT corners.

    Abstract translation: 放大器具有耦合在电压供应节点和输出节点之间的第一上拉通路，以及耦合在输出节点和地电源节点之间的下拉通路。 第二上拉路径耦合在电压供应节点和输出节点之间。 第二上拉路径由反馈信号驱动并被偏置信号偏置。 反相器电路可操作以反转放大器输出节点处的信号以产生反馈信号。 偏置电路被配置为产生偏置信号。 偏置电路被配置为控制到第二上拉路径的下拉路径的相对强度，其中下拉路径以一致地存在于所有PVT角上的方式比第二上拉路径更强 。

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