公开(公告)号：US09449912B1

公开(公告)日：2016-09-20

申请号：US14736353

申请日：2015-06-11

Applicant: STMICROELECTRONICS PTE LTD ,  STMICROELECTRONICS (MALTA) LTD

Inventor： Xueren Zhang ,  Kim-Yong Goh ,  Roseanne Duca

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L24/06 ,  G06K19/07728 ,  G06K19/07745 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49855 ,  H01L23/49888 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2924/0665

Abstract: An integrated circuit (IC) module for an IC card includes a plurality of IC card contacts in side-by-side relation. A dielectric support layer is above the contact layer and has a plurality of openings and a first coefficient of thermal expansion (CTE). An IC die is above the dielectric support layer and includes a plurality of bond pads. A bond wire extends from a respective bond pad to a corresponding contact through an adjacent opening in the dielectric support layer. A respective body of fill material is within each opening and has a second CTE. A mold compound body is above the dielectric support layer, the bodies of fill material, and surrounding the IC die. The mold compound body has a third CTE. The first CTE is closer to the second CTE than to the third CTE.

Abstract translation: 用于IC卡的集成电路（IC）模块包括并排关系的多个IC卡触点。 介电支撑层位于接触层之上，并具有多个开口和第一热膨胀系数（CTE）。 IC芯片在电介质支撑层之上，并且包括多个接合焊盘。 接合线通过介电支撑层中的相邻开口从相应的接合焊盘延伸到相应的接触。 相应的填充材料体在每个开口内并且具有第二CTE。 模具复合体在电介质支撑层上方，填充物体，并围绕IC芯片。 模具复合体具有第三CTE。 第一个CTE比第三个CTE更接近第二个CTE。

公开(公告)号：US20150235929A1

公开(公告)日：2015-08-20

申请号：US14615673

申请日：2015-02-06

Applicant: STMicroelectronics (Malta) Ltd ,  STMicroelectronics S.r.I. ,  STMicroelectronics Pte Ltd

Inventor： Roseanne Duca ,  Valter Motta ,  Xueren Zhang ,  Kim-Yong Goh

IPC: H01L23/495

CPC classification number: H01L23/49568 ,  H01L23/4334 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2924/18301 ,  H01L2924/00014

Abstract: An electronic device includes an integrated circuit chip mounted to a heat slug. The heat slug has a peripheral region having first thickness along a first direction, the peripheral region surrounding a recess region (having a second, smaller, thickness along the first direction) that defines a chip mounting surface along a second direction perpendicular to the first direction. The recess region defines side borders and a nook extends into the heat slug along the side borders. An insulating body embeds the integrated circuit one chip and heat slug. Material of the insulating body fills the nook.

Abstract translation: 一种电子设备包括安装在散热片上的集成电路芯片。 散热片具有沿着第一方向具有第一厚度的周边区域，周边区域围绕沿着垂直于第一方向的第二方向限定芯片安装表面的凹陷区域（具有沿着第一方向的第二较小厚度） 。 凹槽区域限定侧面边界，并且角部沿着侧边缘延伸到热塞中。 绝缘体嵌入集成电路一芯片和散热片。 绝缘体的材料填充角。

公开(公告)号：US20150084171A1

公开(公告)日：2015-03-26

申请号：US14034121

申请日：2013-09-23

Applicant: STMicroelectronics Pte. Ltd.

Inventor： Yiyi Ma ,  Kim-Yong Goh ,  Xueren Zhang

IPC: H01L23/495

CPC classification number: H01L21/4832 ,  H01L21/486 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24101 ,  H01L2224/24247 ,  H01L2224/25171 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82106 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A non-lead (QFN) semiconductor package is disclosed. The package includes a die attach pad and a semiconductor die supported by the die attached pad. The semiconductor die includes a plurality of pads on an active surface thereof. The package further includes a plurality of terminal leads, an encapsulant that encapsulates the semiconductor die, and a redistribution layer including a plurality of interconnections electrically connecting the pads to the terminal leads. A method of making the package is also disclosed.

Abstract translation: 公开了一种非引线（QFN）半导体封装。 封装包括管芯附接焊盘和由管芯附接焊盘支撑的半导体管芯。 半导体管芯包括在其有效表面上的多个焊盘。 该封装还包括多个端子引线，封装半导体管芯的密封剂，以及包括将焊盘电连接到端子引线的多个互连的再分配层。 还公开了制造包装的方法。

公开(公告)号：US20140091443A1

公开(公告)日：2014-04-03

申请号：US14032075

申请日：2013-09-19

Applicant: STMicroelectronics Pte Ltd ,  STMicroelectronics (Malta) Ltd

Inventor： Roseanne Duca ,  Kim-Yong Goh ,  Xueren Zhang ,  Kevin Formosa

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/49541 ,  G01P1/023 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/1815 ,  H05K3/303 ,  H05K3/3421 ,  H05K2201/09781 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2224/45099

Abstract: A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package.

Abstract translation: 半导体器件的表面贴装封装具有：封装，容纳至少一个包含半导体材料的管芯; 以及电接触引线，从封装凸出以电耦合到电路板的接触焊盘; 封装具有设计成面向电路板的顶表面的主面，该主面具有设计成用于机械耦合到电路板的耦合特征，以增加安装封装的谐振频率。 耦合特征设想至少一个第一耦合凹槽，其限定在从主面开始的封装内，被设计成由固定到电路板的对应耦合元件接合，从而限制安装的封装的移动。