公开(公告)号：US20170301681A1

公开(公告)日：2017-10-19

申请号：US15377861

申请日：2016-12-13

Applicant: STMicroelectronics SA

Inventor： Stephane Denorme ,  Philippe Candelier

IPC: H01L27/112 ,  H01L23/00 ,  H01L23/525 ,  H01L27/02 ,  G11C17/16

CPC classification number: H01L27/11206 ,  G11C11/005 ,  G11C17/10 ,  G11C17/16 ,  H01L23/5252 ,  H01L23/57 ,  H01L27/0203

Abstract: A configurable read only memory (ROM) including a number of memory cells. The memory cells include first-type memory cells that are electrically-programmable antifuses and second-type memory cells that are antifuses programmed by masking.

公开(公告)号：US20130294142A1

公开(公告)日：2013-11-07

申请号：US13887167

申请日：2013-05-03

Applicant: STMICROELECTRONICS SA

Inventor： Philippe Candelier ,  Joel Damiens ,  Elise Leroux

IPC: G11C17/16

CPC classification number: G11C17/165 ,  G11C17/18 ,  H01L27/101 ,  H01L27/11206

Abstract: A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time.

公开(公告)号：US11355503B2

公开(公告)日：2022-06-07

申请号：US16708912

申请日：2019-12-10

Applicant: STMicroelectronics SA

Inventor： Stephane Denorme ,  Philippe Candelier

IPC: H01L27/112 ,  H01L23/528 ,  G11C17/18 ,  H01L27/02 ,  H01L29/423

Abstract: A device includes at least three memory cells. For each cell, there is a first doped semiconductor area and a switch coupling the cell to the first area. First doped semiconductor zones connect the first areas together. A memory can include a number of the devices. For example, the cells can be arranged in a matrix, each device defining a row of the matrix.

公开(公告)号：US20220139491A1

公开(公告)日：2022-05-05

申请号：US17647793

申请日：2022-01-12

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics SA

Inventor： Stephane Denorme ,  Philippe Candelier ,  Joel Damiens ,  Fabrice Marinet

IPC: G11C29/52 ,  G11C17/12

Abstract: A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.

公开(公告)号：US09881928B2

公开(公告)日：2018-01-30

申请号：US15413497

申请日：2017-01-24

Applicant: STMicroelectronics SA

Inventor： Stéphane Denorme ,  Philippe Candelier

IPC: H01L27/112 ,  H01L21/84 ,  H01L23/525 ,  H01L27/12 ,  H01L21/28 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/06

CPC classification number: H01L27/11206 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/7624 ,  H01L21/823418 ,  H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/66181 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a silicon-on-insulator substrate that includes a semiconductor film located above a buried insulating layer. A first electrode of a silicide material overlies the semiconductor film. A sidewall insulating material is disposed along sidewalls of the first electrode. A dielectric layer is located between the first electrode and the semiconductor film. A second electrode includes a silicided zone of the semiconductor film, which is located alongside the sidewall insulating material and extends at least partially under the dielectric layer and the first electrode. The first electrode, the dielectric layer and the second electrode form a capacitor that is part of a circuit of the integrated circuit.

公开(公告)号：US20160343720A1

公开(公告)日：2016-11-24

申请号：US14952662

申请日：2015-11-25

Applicant: STMicroelectronics SA

Inventor： Stéphane Denorme ,  Philippe Candelier

IPC: H01L27/112 ,  H01L29/49 ,  H01L29/40 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/11206 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/7624 ,  H01L21/823418 ,  H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/66181 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a silicon on insulator substrate having a semiconductor film located above a buried insulating layer. At least one memory cell of the one-time-programmable type includes an MOS capacitor having a first electrode region including a gate region at least partially silicided and flanked by an insulating lateral region, a dielectric layer located between the gate region and the semiconductor film, and a second electrode region including a silicided zone of the semiconductor film, located alongside the insulating lateral region and extending at least partially under the dielectric layer.

Abstract translation: 集成电路包括具有位于掩埋绝缘层上方的半导体膜的绝缘体上硅衬底。 一次可编程类型的至少一个存储单元包括具有第一电极区域的MOS电容器，该第一电极区域包括至少部分硅化并且侧壁为绝缘横向区域的栅极区域，位于栅极区域和半导体膜之间的电介质层 以及包括半导体膜的硅化物区域的第二电极区域，位于绝缘横向区域旁边并且至少部分地延伸到介电层下方。

公开(公告)号：US20160307640A1

公开(公告)日：2016-10-20

申请号：US14956963

申请日：2015-12-02

Applicant: STMicroelectronics SA

Inventor： Philippe Candelier ,  Antoine Benoist ,  Stephane Denorme ,  Joel Damiens

IPC: G11C17/16 ,  G11C17/18

CPC classification number: G11C17/165 ,  G11C5/145 ,  G11C5/147 ,  G11C7/04 ,  G11C17/16 ,  G11C17/18

Abstract: A memory cell of the one-time-programmable type is programmed by application of a programming voltage having a value sufficient to obtain a breakdown of a dielectric of a capacitor within the cell. A programming circuit generates the programming voltage as a variable voltage that varies as a function of a temperature (T) of the cell. In particular, the programming voltage varies based on a variation law decreasing as a function of the temperature.

Abstract translation: 通过施加具有足以获得电池内的电容器的电介质的击穿的编程电压来编程一次性可编程类型的存储单元。 编程电路产生编程电压作为可变电压，其随电池的温度（T）而变化）。 特别地，编程电压根据作为温度的函数的变化规律减小而变化。

公开(公告)号：US09406372B2

公开(公告)日：2016-08-02

申请号：US13836690

申请日：2013-03-15

Applicant: STMicroelectronics SA

Inventor： Philippe Candelier ,  Laurent Dedieu ,  Noureddine Larhriq

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/24 ,  G11C8/20 ,  G11C11/41 ,  G11C16/22

CPC classification number: G11C11/419 ,  G11C7/24 ,  G11C8/20 ,  G11C11/41 ,  G11C16/22

Abstract: A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope.