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公开(公告)号：US20130311821A1
公开(公告)日：2013-11-21
申请号：US13996717
申请日：2012-03-30
IPC分类号： G06F11/20
CPC分类号： G06F11/2094 , G06F11/1658 , G06F11/1666 , G06F11/20 , G06F2201/815
摘要： Systems and techniques for virtual device sharing. A failure of one of a plurality of memory devices corresponding to a first rank in a memory system is detected. The memory system has a plurality of ranks, each rank having a plurality of memory devices used to store a cache line. A portion of the cache line corresponding to the failed memory device is stored in a memory device in a second rank in the memory system and the remaining portion of the cache line in the first rank of the memory system.
摘要翻译： 用于虚拟设备共享的系统和技术。 检测到与存储器系统中的第一等级对应的多个存储器件中的一个的故障。 存储器系统具有多个等级，每个等级具有用于存储高速缓存行的多个存储器件。 对应于故障存储器件的高速缓存线的一部分被存储在存储器系统中的第二等级的存储器件中，并且存储器系统的第一级中的高速缓存行的剩余部分被存储。
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12.发明申请公开(公告)号：US20130007046A1
公开(公告)日：2013-01-03
申请号：US13175772
申请日：2011-07-01
IPC分类号： G06F17/30
CPC分类号： G06F13/4022
摘要： Methods and apparatus relating to dynamically routing data responses directly to a requesting processor core are described. In one embodiment, data returned in response to a data request is to be directly transmitted to a requesting agent based on information stored in a route back table. Other embodiments are also disclosed.
摘要翻译： 描述了将数据响应直接动态地路由到请求处理器核心的方法和装置。 在一个实施例中，响应于数据请求返回的数据将基于存储在路由表中的信息直接发送到请求代理。 还公开了其他实施例。
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13.发明授权公开(公告)号：US07500240B2
公开(公告)日：2009-03-03
申请号：US10047809
申请日：2002-01-15
申请人： Ken Shoemaker , Sailesh Kottapalli , Kin-Kee Sit
发明人： Ken Shoemaker , Sailesh Kottapalli , Kin-Kee Sit
CPC分类号： G06F9/3802 , G06F9/3851 , G06F9/3885
摘要： An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit to receive a first thread and a second instruction fetch unit to receive a second thread. A multi-thread scheduler coupled to the instruction fetch units and a execution unit. The multi-thread scheduler determines the width of the execution unit and the execution unit executes the threads accordingly.
摘要翻译： 提供多线程处理器。 多线程处理器包括接收第一线程的第一指令获取单元和用于接收第二线程的第二指令获取单元。 耦合到指令提取单元和执行单元的多线程调度器。 多线程调度器确定执行单元的宽度，并且执行单元相应地执行线程。
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14.发明申请Method and apparatus for instruction pointer storage element configuration in a simultaneous multithreaded processor 审中-公开同时多线程处理器中指令指针存储元件配置的方法和装置公开(公告)号：US20080215864A1
公开(公告)日：2008-09-04
申请号：US11638315
申请日：2006-12-12
申请人： Sailesh Kottapalli
发明人： Sailesh Kottapalli
IPC分类号： G06F9/312
CPC分类号： G06F9/3851 , G06F9/3867
摘要： A simultaneous multithreaded processor that reduces the number of hardware components necessary as well as the complexity of design over current systems is disclosed. As opposed to requiring individual storage elements for saving instruction pointer information for each re-steer logic component within a processor pipeline, the present invention allows for instruction pointer information of an inactive thread to be stored in a single, ‘inactive thread’ storage element until the thread becomes active again.
摘要翻译： 公开了一种同时多线程处理器，其减少了所需的硬件组件的数量以及当前系统上的设计的复杂性。 与在处理器流水线内为每个重新转向逻辑组件需要单独的存储元件来保存指令指针信息相反，本发明允许将一个非活动线程的指令指针信息存储在一个“非线程线程”存储元件中，直到 线程再次变为活动状态。
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15.发明申请Method and apparatus for handling predicated instructions in an out-of-order processor 审中-公开用于处理乱序处理器中的预测指令的方法和装置公开(公告)号：US20050066151A1
公开(公告)日：2005-03-24
申请号：US10666343
申请日：2003-09-19
申请人： Sailesh Kottapalli
发明人： Sailesh Kottapalli
CPC分类号： G06F9/3017 , G06F9/30072 , G06F9/384
摘要： A method and apparatus for permitting out-of-order execution of predicated instructions is disclosed. In one embodiment, a predicated instruction may be decoded into a related predicated instruction and a move instruction contingent on the complementary value of the predicate of the predicated instruction. The destination register of both the related predicated instruction and the move instruction may be mapped to the same physical register, and only one of the two instructions may update machine state with its results.
摘要翻译： 公开了一种用于允许无序执行预定指令的方法和装置。 在一个实施例中，预测指令可以被解码成相关的预测指令和移动指令，这取决于预测指令的谓词的互补值。 相关的预测指令和移动指令的目标寄存器可以被映射到相同的物理寄存器，并且两个指令中的仅一个可以用其结果来更新机器状态。
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公开(公告)号：US10387151B2
公开(公告)日：2019-08-20
申请号：US13250223
申请日：2011-09-30
摘要： Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value.
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公开(公告)号：US07496732B2
公开(公告)日：2009-02-24
申请号：US10739686
申请日：2003-12-17
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3824 , G06F9/3826 , G06F9/3838 , G06F9/3842 , G06F9/3861
摘要： A method and apparatus for using result-speculative data under run-ahead speculative execution is disclosed. In one embodiment, the uncommitted target data from instructions being run-ahead executed may be saved into an advance data table. This advance data table may be indexed by the lines in the instruction buffer containing the instructions for run-ahead execution. When the instructions are re-executed subsequent to the run-ahead execution, valid target data may be retrieved from the advance data table and supplied as part of a zero-clock bypass to support parallel re-execution. This may achieve parallel execution of dependent instructions. In other embodiments, the advance data table may be content-addressable-memory searchable on target registers and supply target data to general speculative execution.
摘要翻译： 公开了一种在预先推测执行下使用结果推测数据的方法和装置。 在一个实施例中，来自正在执行的预定指令的未提交的目标数据可以被保存到提前数据表中。 该提前数据表可以由包含用于预先执行的指令的指令缓冲器中的行进行索引。 当在超前执行之后重新执行指令时，可以从提前数据表检索有效的目标数据，并作为零时钟旁路的一部分提供以支持并行重新执行。 这可以实现依赖指令的并行执行。 在其他实施例中，提前数据表可以是内容寻址存储器，可在目标寄存器上搜索，并将目标数据提供给一般推测执行。
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公开(公告)号：US20050210905A1
公开(公告)日：2005-09-29
申请号：US10808882
申请日：2004-03-24
申请人： James Burns , Sailesh Kottapalli
发明人： James Burns , Sailesh Kottapalli
CPC分类号： G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296 , H01L23/34 , H01L2924/0002 , Y02D10/126 , Y02D10/171 , Y02D10/172 , H01L2924/00
摘要： A system may include a first portion and a processor. The first portion may include a first thermal sensor to provide first thermal data. The processor may include a core, a core thermal sensor to provide core thermal data, and an electrical power sensor to provide electrical data. The processor may also include a power management unit to selectively throttle the core based on the first thermal data, the core thermal data, and the electrical data.
摘要翻译： 系统可以包括第一部分和处理器。 第一部分可以包括第一热传感器以提供第一热数据。 处理器可以包括芯，提供核心热数据的核心热传感器，以及提供电数据的电功率传感器。 处理器还可以包括功率管理单元，用于基于第一热数据，核心热数据和电数据来选择性地调节核心。
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19.发明授权High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle 有权多线程处理器中的高指令提取带宽使用临时指令高速缓存在随后的时钟周期内传送部分高速缓存行公开(公告)号：US06898694B2
公开(公告)日：2005-05-24
申请号：US09896346
申请日：2001-06-28
CPC分类号： G06F9/3806 , G06F9/3802 , G06F9/3851
摘要： The present invention provides a mechanism for supporting high bandwidth instruction fetching in a multi-threaded processor. A multi-threaded processor includes an instruction cache (I-cache) and a temporary instruction cache (TIC). In response to an instruction pointer (IP) of a first thread hitting in the I-cache, a first block of instructions for the thread is provided to an instruction buffer and a second block of instructions for the thread are provided to the TIC. On a subsequent clock interval, the second block of instructions is provided to the instruction buffer, and first and second blocks of instructions from a second thread are loaded into a second instruction buffer and the TIC, respectively.
摘要翻译： 本发明提供一种用于在多线程处理器中支持高带宽指令提取的机制。 多线程处理器包括指令高速缓存（I-cache）和临时指令高速缓存（TIC）。 响应于在I缓存中击中的第一线程的指令指针（IP），将线程的第一指令块提供给指令缓冲器，并且向TIC提供用于线程的第二指令块。 在随后的时钟间隔中，第二指令块被提供给指令缓冲器，并且来自第二线程的第一和第二指令块分别被加载到第二指令缓冲器和TIC中。
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20.发明授权公开(公告)号：US06721873B2
公开(公告)日：2004-04-13
申请号：US09753060
申请日：2000-12-29
申请人： Sailesh Kottapalli , Udo Walterscheidt , Andrew Sun , Thomas Yeh , Kinkee Sit
发明人： Sailesh Kottapalli , Udo Walterscheidt , Andrew Sun , Thomas Yeh , Kinkee Sit
IPC分类号： G06F938
CPC分类号： G06F9/3885 , G06F9/3853
摘要： A method and apparatus for improving dispersal performance of instruction threads is described. In one embodiment, the dispersal logic determines whether the instructions supplied to it include any NOP instructions. When a NOP instruction is detected, the dispersal logic places the NOP into a no-op port for execution. All other instructions are distributed to the proper execution pipes in a normal manner. Because the NOP instructions do not use the execution resources of other instructions, all instruction threads can be executed in one cycle.
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