公开(公告)号：US11289438B2

公开(公告)日：2022-03-29

申请号：US16985445

申请日：2020-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiseok Hong ,  Unbyoung Kang ,  Myungsung Kang ,  Taehun Kim ,  Sangcheon Park ,  Hyuekjae Lee ,  Jihwan Hwang

IPC: H01L29/40 ,  H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48

Abstract: According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

公开(公告)号：US10790186B2

公开(公告)日：2020-09-29

申请号：US15984524

申请日：2018-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiseok Hong ,  Chan-Sic Yoon ,  Ilyoung Moon ,  Jemin Park ,  Kiseok Lee ,  Jung-Hoon Han

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A method of fabricating a semiconductor device includes providing a substrate, and forming an interlayered insulating layer on the substrate. The method includes forming a preliminary via hole in the interlayered insulating layer. The method includes forming a passivation spacer on an inner side surface of the preliminary via hole. The method includes forming a via hole using the passivation spacer as an etch mask. The method includes forming a conductive via in the via hole. The passivation spacer includes an insulating material different from an insulating material included in the interlayered insulating layer.

公开(公告)号：US11676925B2

公开(公告)日：2023-06-13

申请号：US17500079

申请日：2021-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiseok Hong ,  Hyuekjae Lee ,  Jongpa Hong ,  Jihwan Hwang ,  Taehun Kim

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L24/13 ,  H01L23/481 ,  H01L24/05 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/1357 ,  H01L2224/13541 ,  H01L2924/1434

Abstract: A semiconductor package includes a first semiconductor chip having a through-electrode and an upper connection pad on an upper surface of the first semiconductor chip that is connected to the through-electrode; a second semiconductor chip stacked on the first semiconductor chip, and having a lower connection pad on a lower surface of the second semiconductor chip; a non-conductive film between the first semiconductor chip and the second semiconductor chip, with the non-conductive film including voids having an average diameter of 1 μm to 100 μm, the voids having a volume fraction of 0.1 to 5 vol %; and a connection conductor that penetrates the non-conductive film and connects the upper connection pad and the lower connection pad.

公开(公告)号：US11244927B2

公开(公告)日：2022-02-08

申请号：US16833761

申请日：2020-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuekjae Lee ,  Jihoon Kim ,  Jihwan Suh ,  Soyoun Lee ,  Jiseok Hong ,  Taehun Kim ,  Jihwan Hwang

IPC: H01L23/16 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31

Abstract: Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads.

公开(公告)号：US20210391259A1

公开(公告)日：2021-12-16

申请号：US17129083

申请日：2020-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyoung Ahn ,  Seunguk Han ,  Sunghwan Kim ,  Seoryong Park ,  Kiseok Lee ,  Yoonyoung Choi ,  Taehee Han ,  Jiseok Hong

IPC: H01L23/528

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.

公开(公告)号：US11158594B2

公开(公告)日：2021-10-26

申请号：US17007223

申请日：2020-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiseok Hong ,  Hyuekjae Lee ,  Jongpa Hong ,  Jihwan Hwang ,  Taehun Kim

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/48

Abstract: A semiconductor package includes a first semiconductor chip having a through-electrode and an upper connection pad on an upper surface of the first semiconductor chip that is connected to the through-electrode; a second semiconductor chip stacked on the first semiconductor chip, and having a lower connection pad on a lower surface of the second semiconductor chip; a non-conductive film between the first semiconductor chip and the second semiconductor chip, with the non-conductive film including voids having an average diameter of 1 μm to 100 μm, the voids having a volume fraction of 0.1 to 5 vol %; and a connection conductor that penetrates the non-conductive film and connects the upper connection pad and the lower connection pad.

公开(公告)号：US10410916B2

公开(公告)日：2019-09-10

申请号：US16106266

申请日：2018-08-21

Applicant: Samsung ELectronics Co., Ltd.

Inventor： Jiseok Hong ,  Kiseok Lee ,  Jemin Park ,  Yoosang Hwang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes an interlayer insulation layer on a semiconductor substrate, a via plug and a wiring line on the via plug, in the interlayer insulation layer, the via plug and the wiring line coupled with each other and forming a stepped structure. The semiconductor device includes a first air-gap region between the interlayer insulation layer and the via plug, and a second air-gap region between the interlayer insulation layer and the wiring line. The first air-gap region and the second air-gap region are not vertically overlapped with each other.