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    INTEGRATED CIRCUIT DEVICE
    11.
    发明申请
    INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20250107179A1

    公开(公告)日：2025-03-27

    申请号：US18663867

    申请日：2024-05-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Wonkeun CHUNG ,  Geunwoo KIM ,  Wandon KIM ,  Hyoseok CHOI

    IPC: H01L29/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

    Abstract: Provided is an integrated circuit device and a method of manufacturing same, the integrated circuit device including: a fin-type active region on a substrate, a pair of insulating spacers on the fin-type active region and the substrate and defining a first space, a gate dielectric film contacting the gate line in the first space, a gate contact plug having a conductive bottom surface contacting a top contact portion of the gate line in the first space, and a capping insulating pattern including an insulating bottom surface, a pair of first insulating sidewalls, and a second insulating sidewall, the insulating bottom surface contacting a local top surface of the gate line in the first space, the pair of first insulating sidewalls contacting the pair of insulating spacers, and the second insulating sidewall contacting the gate contact plug, wherein an insulating top surface of the capping insulating pattern and a conductive top surface of the gate contact plug extend along one plane.

    SEMICONDUCTOR PACKAGE
    13.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240136307A1

    公开(公告)日：2024-04-25

    申请号：US18380928

    申请日：2023-10-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Geunwoo KIM

    IPC: H01L23/00 ,  H01L23/498

    CPC classification number: H01L23/562 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/06517 ,  H01L2224/14517 ,  H01L2224/16227

    Abstract: A semiconductor package includes a semiconductor chip including a semiconductor substrate having a first surface and a second surface opposite to the first surface, a chip pad located on the first surface and including a conductive layer, a support pad positioned on the first surface, spaced apart from the chip pad and including an insulating layer, a support bump connected to the support pad, a wiring substrate disposed to face the semiconductor substrate, a support bonding on trace (BOT) pad disposed on the wiring substrate and bonded to the support bump, and a dummy area disposed on the wiring substrate and spaced apart from the support BOT pad.

    SEMICONDUCTOR DEVICE
    14.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220392899A1

    公开(公告)日：2022-12-08

    申请号：US17886878

    申请日：2022-08-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yoon Tae HWANG ,  Sunjung LEE ,  Heonbok LEE ,  Geunwoo KIM ,  Wandon KIM

    IPC: H01L27/092 ,  H01L21/8238

    Abstract: A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

    SEMICONDUCTOR DEVICE
    15.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220069129A1

    公开(公告)日：2022-03-03

    申请号：US17321960

    申请日：2021-05-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Geunwoo KIM ,  Wandon KIM ,  Heonbok LEE ,  Yoontae HWANG

    IPC: H01L29/78 ,  H01L29/417

    Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction; a gate structure extending across the fin-type active region in a second direction, different from the first direction; a source/drain region in the fin-type active region on one side of the gate structure; and first and second contact structures connected to the source/drain region and the gate structure, respectively, wherein at least one of the first and second contact structures includes a seeding layer on at least one of the gate structure and the source/drain region and including a first crystalline metal, and a contact plug on the seeding layer and including a second crystalline metal different from the first crystalline metal, and the second crystalline metal is substantially lattice-matched to the first crystalline metal at an interface between the seeding layer and the contact plug.

    SEMICONDUCTOR PACKAGE
    16.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210391280A1

    公开(公告)日：2021-12-16

    申请号：US17162444

    申请日：2021-01-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Geunwoo KIM

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31

    Abstract: A semiconductor package may include a package substrate, a molded interposer package (MIP) and a first stiffener. The MIP may be arranged on the package substrate. The MIP may include an interposer, at least one first semiconductor chip and at least one second semiconductor chip molded by a molding member. The first stiffener may be attached to any one of outer surfaces of the MIP. The first stiffener may be spaced apart from the upper surface of the package substrate to suppress a warpage of the MIP. Thus, central conductive bumps between the MIP and the package substrate may not be upwardly floated to improve an electrical connection between the central conductive bumps and the package substrate. Further, a short between edge conductive bumps between the MIP and the package substrate may not be generated.

    ELECTRONIC DEVICE INCLUDING ANTENNA
    17.
    发明申请
    ELECTRONIC DEVICE INCLUDING ANTENNA 审中-公开
    包括天线的电子设备

    公开(公告)号：US20160141746A1

    公开(公告)日：2016-05-19

    申请号：US14940402

    申请日：2015-11-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Geunwoo KIM ,  Hyun KIM ,  Minho SOH ,  Changgwon CHUNG

    IPC: H01Q1/27 ,  H01Q1/50

    CPC classification number: H01Q1/273 ,  G04R60/04 ,  G04R60/06 ,  H01Q1/50

    Abstract: An electronic device is provided. The electronic device includes a body including a communication module, and at least one first conductive contact configured to transmit electrical signals to and receive electrical signals from the communication module; and at least one strap removably connected to the body, the at least one strap including an antenna therein, and at least one second conductive contact configured to transmit electrical signals to and receive electrical signals from the antenna, the one strap being configured to removably connect to the body, such that at least a portion of the at least one first conductive contact is electrically connected to the at least one second conductive contact.

    Abstract translation: 提供电子设备。 电子设备包括一个主体，它包括一个通信模块，以及至少一个第一导电触点，被配置为将电信号传送到通信模块并从该通信模块接收电信号; 以及至少一个可移除地连接到所述主体的带，所述至少一个带包括其中的天线，以及至少一个第二导电触点，其被配置成将电信号传输到所述天线并从所述天线接收电信号，所述一个带被配置为可移除地连接 使得所述至少一个第一导电接触件的至少一部分电连接到所述至少一个第二导电接触件。

    SEMICONDUCTOR PACKAGE
    18.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240234342A9

    公开(公告)日：2024-07-11

    申请号：US18380928

    申请日：2023-10-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Geunwoo KIM

    IPC: H01L23/00 ,  H01L23/498

    CPC classification number: H01L23/562 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/06517 ,  H01L2224/14517 ,  H01L2224/16227

    Abstract: A semiconductor package includes a semiconductor chip including a semiconductor substrate having a first surface and a second surface opposite to the first surface, a chip pad located on the first surface and including a conductive layer, a support pad positioned on the first surface, spaced apart from the chip pad and including an insulating layer, a support bump connected to the support pad, a wiring substrate disposed to face the semiconductor substrate, a support bonding on trace (BOT) pad disposed on the wiring substrate and bonded to the support bump, and a dummy area disposed on the wiring substrate and spaced apart from the support BOT pad.

    SEMICONDUCTOR PACKAGE
    19.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240145329A1

    公开(公告)日：2024-05-02

    申请号：US18320527

    申请日：2023-05-19

    Applicant: Samsung Electronics Co. Ltd.

    Inventor： Geunwoo KIM ,  Kyung Don MUN

    IPC: H01L23/36 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10

    CPC classification number: H01L23/36 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/5383 ,  H01L25/105 ,  H01L24/08 ,  H01L2224/08225

    Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, a heat dissipation layer on the first semiconductor chip and in contact with an upper surface of the first semiconductor chip, a second redistribution substrate on the heat dissipation layer, a molding layer surrounding the first semiconductor chip and the heat dissipation layer between the first redistribution substrate and the second redistribution substrate, through electrodes vertically penetrating the molding layer and electrically connecting the first redistribution substrate and the second redistribution substrate, the through electrodes being spaced apart from the first semiconductor chip and the heat dissipation layer, and dummy patterns vertically penetrating the molding layer and in contact with a side surface of the first semiconductor chip and a side surface of the heat dissipation layer. The first redistribution substrate includes a first insulating layer, first wiring patterns in the first insulating layer and electrically connecting the first semiconductor chip and the through electrodes, and second wiring patterns in the first insulating layer, electrically connected to the dummy patterns, and electrically insulated from the first wiring patterns.

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