公开(公告)号：US11599301B2

公开(公告)日：2023-03-07

申请号：US17245325

申请日：2021-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haesuk Lee ,  Reum Oh ,  Youngcheon Kwon ,  Beomyong Kil ,  Jemin Ryu ,  Jihyun Choi

IPC: G06F3/06 ,  G11C7/22

Abstract: A semiconductor memory device includes an interface semiconductor die, at least one memory semiconductor die, and through-silicon vias connecting the interface semiconductor die and the memory semiconductor die. The interface semiconductor die includes command pins to receive command signals transferred from a memory controller and an interface command decoder to decode the command signals. The memory semiconductor die includes a memory integrated circuit configured to store data and a memory command decoder to decode the command signals transferred from the interface semiconductor die. The interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller. The interface and memory command decoders generate interface and memory clock enable signals to control clock supply with respect to the interface and memory semiconductor dies based on a power mode command transferred through the plurality of command pins from the memory controller.

公开(公告)号：US10740033B2

公开(公告)日：2020-08-11

申请号：US16197877

申请日：2018-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： So-young Kim ,  Reum Oh ,  Haesuk Lee

IPC: G06F3/06 ,  H01L25/18 ,  G11C11/4093 ,  G11C11/4076 ,  H01L23/48 ,  H01L25/065 ,  G11C11/408

Abstract: A memory die of a memory device includes a first first-in first-out (FIFO) circuit that samples data output from a memory cell array and outputs the data to a buffer die through a first through silicon via, based on a control signal transmitted from the buffer die. A buffer die of the memory device includes a second FIFO circuit that samples the data output from the first FIFO unit based on the control signal transmitted from the memory die through a second through silicon via, a calibration circuit that generates a delay code, based on a latency of a path from the buffer die to the first FIFO circuit and from the first FIFO circuit to the second FIFO circuit, and a delay control circuit that generates the control signal transmitted to the memory die through a third through silicon via, based on the read command and the delay code.

公开(公告)号：US20230138048A1

公开(公告)日：2023-05-04

申请号：US18145186

申请日：2022-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngcheon Kwon ,  Jaesan Kim ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  H01L25/18

Abstract: A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.

公开(公告)号：US11636885B2

公开(公告)日：2023-04-25

申请号：US17574174

申请日：2022-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngcheon Kwon ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee ,  Jihyun Choi

IPC: G11C7/22 ,  G11C7/10

Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

公开(公告)号：US11416178B2

公开(公告)日：2022-08-16

申请号：US17014667

申请日：2020-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsung Shin ,  Sanghyuk Kwon ,  Youngcheon Kwon ,  Sukhan Lee ,  Haesuk Lee

IPC: G06F3/06 ,  G06N3/02

Abstract: A memory device includes a memory bank including a plurality of banks, each including a memory cell array; a calculation logic including a plurality of processor-in-memory (PIM) circuits arranged in correspondence to the banks, each of the plurality of PIM circuits performing calculation processing using at least one selected from data provided from a host and information read from a corresponding bank among the banks; and a control logic configured to control a memory operation on the memory bank in response to a command and/or an address, each received from the host, or to control the calculation logic to perform the calculation processing, wherein reading operations are respectively performed in parallel on the banks for the calculation processing, offsets having different values are respectively configured for the banks, and information is read from different positions in respective memory cell arrays of the banks and provided to the PIM circuits.

公开(公告)号：US20210217461A1

公开(公告)日：2021-07-15

申请号：US16994796

申请日：2020-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Seongil O ,  Haesuk Lee

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4074

Abstract: A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.

公开(公告)号：US20240282353A1

公开(公告)日：2024-08-22

申请号：US18654443

申请日：2024-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngcheon KWON ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee ,  Jihyun Choi

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084

Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

公开(公告)号：US11664061B2

公开(公告)日：2023-05-30

申请号：US17722494

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngcheon Kwon ,  Sanghyuk Kwon ,  Kyomin Sohn ,  Jaeyoun Youn ,  Haesuk Lee

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/406 ,  G11C11/4085

Abstract: A memory device according to some aspects of the inventive concepts includes a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which wordlines included in each of the plurality of banks is activated, and configured to control a refresh operation in which at least one bank is refreshed, based on a PE enable signal configured to selectively enable the at least one PE.

公开(公告)号：US20220130841A1

公开(公告)日：2022-04-28

申请号：US17496498

申请日：2021-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaesan Kim ,  Seunghan Woo ,  Haesuk Lee ,  Youngcheon Kwon ,  Reum Oh

IPC: H01L27/108 ,  H01L23/48 ,  H01L23/528 ,  H01L29/8605 ,  H01L29/94

Abstract: A semiconductor device includes a semiconductor structure including a semiconductor substrate having an active zone with a channel; a through silicon via (TSV) structure including a power TSV configured to transmit power and a signal TSV configured to transmit a signal; and a keep-out zone located a predetermined distance away from the TSV structure and bounded by the active zone. The TSV structure penetrates the semiconductor substrate. The keep-out zone includes a first element area a first distance away from the power TSV, and a second element area a second distance away from the signal TSV.

公开(公告)号：US20220075541A1

公开(公告)日：2022-03-10

申请号：US17335307

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngcheon Kwon ,  Jaesan Kim ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee

IPC: G06F3/06 ,  H01L25/18 ,  G11C7/10 ,  G11C7/22

Abstract: A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.