公开(公告)号：US20240321980A1

公开(公告)日：2024-09-26

申请号：US18596772

申请日：2024-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun LEE ,  Heonjong SHIN ,  Jaehyun KANG ,  Seonbae KIM ,  Wangseop LIM ,  Seunghyun HWANG

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: An integrated circuit device includes a substrate having a main surface and fin-type active regions protruding in a vertical direction from the main surface and extending lengthwise in a first horizontal direction, gate lines extending parallel to one another in a second horizontal direction perpendicular to the first horizontal direction and crossing the fin-type active regions, source/drain regions on the fin-type active regions between the gate lines, an inter-gate insulation layer covering the source/drain regions between the gate lines, active contacts on and in contact with the source/drain regions, and a buried insulation block between adjacent ones of the source/drain regions in the second horizontal direction, the buried insulation block penetrating through at least a portion of the inter-gate insulation layer and having a top surface in contact with a first active contact of the active contacts.

公开(公告)号：US20240136398A1

公开(公告)日：2024-04-25

申请号：US18323715

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junmo PARK ,  Wookhyun KWON ,  Yeonho PARK ,  Jongmin SHIN ,  Heonjong SHIN ,  Jongmin JUN ,  Kyubong CHOI

IPC: H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/24 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern, a source/drain pattern, a gate electrode, and an insulation pattern. The channel pattern may include semiconductor patterns that are spaced apart from each other and vertically stacked. A lowermost one of the semiconductor patterns may be a first semiconductor pattern. The source/drain pattern may be connected to the semiconductor patterns. The gate electrode may be on the semiconductor patterns and may include a plurality of inner electrodes below the semiconductor patterns except the first semiconductor pattern. The insulation pattern may be between the first semiconductor pattern and the active pattern. The insulation pattern may include a dielectric pattern and a protection layer. The protection layer may be between the dielectric pattern and the first semiconductor pattern. The protection layer may be between the dielectric pattern and the active pattern.

公开(公告)号：US20230231023A1

公开(公告)日：2023-07-20

申请号：US18085331

申请日：2022-12-20

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Doohyun LEE ,  Heonjong SHIN ,  Seonbae KIM ,  Jinyoung PARK ,  Hyunho PARK ,  Jimin YU ,  Jaeran JANG

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/401 ,  H01L29/66439

Abstract: A semiconductor device includes a substrate, active regions extending in a first horizontal direction on the substrate, and including first and second active regions spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, and third and fourth active regions spaced apart from each other in the second horizontal direction, first to fourth source/drain regions on the first to fourth active regions, first to fourth contact plugs connected to the first to fourth source/drain regions, a first isolation insulating pattern disposed between the first and second contact plugs, and a second isolation insulating pattern disposed between the third and fourth contact plugs, wherein a first length of the first isolation insulating pattern is smaller than a second length of the second isolation insulating pattern in a vertical direction.

公开(公告)号：US20210193808A1

公开(公告)日：2021-06-24

申请号：US17175850

申请日：2021-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inchan HWANG ,  Heonjong SHIN ,  Sunghun JUNG ,  Doohyun LEE ,  Hwichan JUN ,  Hakyoon AHN

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L21/285 ,  H01L29/06 ,  H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/78

Abstract: A semiconductor device is disclosed. The semiconductor device may include a substrate including a first active pattern, the first active pattern vertically protruding from a top surface of the substrate, a first source/drain pattern filling a first recess, which is formed in an upper portion of the first active pattern, a first metal silicide layer on the first source/drain pattern, the first metal silicide layer including a first portion and a second portion, which are located on a first surface of the first source/drain pattern, and a first contact in contact with the second portion of the first metal silicide layer. A thickness of the first portion may be different from a thickness of the second portion.

公开(公告)号：US20250096133A1

公开(公告)日：2025-03-20

申请号：US18645765

申请日：2024-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seowoo NAM ,  Heonjong SHIN ,  Juneyoung PARK ,  Sanghee LEE

IPC: H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit device includes a fin-type active region extending in a first horizontal direction on a substrate, a plurality of nanosheets facing a fin top of the fin-type active region, a gate line on the fin-type active region, the gate line surrounding each of the nanosheets and extending in a second horizontal direction, and a source/drain region on the fin-type active region. The gate line includes a main gate portion on the nanosheet stack, a first sub gate portion, a second sub gate portion, and a third sub gate portion. A width of the first sub gate portion in the first horizontal direction is greater than or equal to a width of the third sub gate portion in the first horizontal direction and the width of the first sub gate portion is less than a width of the second sub gate portion in the first horizontal direction.

公开(公告)号：US20240321689A1

公开(公告)日：2024-09-26

申请号：US18441327

申请日：2024-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juneyoung PARK ,  Heonjong SHIN ,  Jongmin SHIN ,  Jaeran JANG

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is a semiconductor device including an active device layer including a plurality of source/drain patterns, a plurality of insulating layers on the active device layer, a back end of line (BEOL) structure on the plurality of insulating layers and configured to supply electric power to the active device layer, an intermediate layer between the plurality of insulating layers and the BEOL structure, and at least one power via penetrating through the intermediate layer and at least a part in each of the plurality of insulating layers in a vertical direction. The at least one power via electrically connects the BEOL structure and the active device layer. At least a part of a side surface of the at least one power via is in contact with the intermediate layer.

公开(公告)号：US20230223451A1

公开(公告)日：2023-07-13

申请号：US18073682

申请日：2022-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun LEE ,  Heonjong SHIN ,  Seonbae KIM ,  Jinyoung PARK ,  Hyunho PARK ,  Jimin YU ,  Jaeran JANG

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/401 ,  H01L29/66439

Abstract: A semiconductor device includes an active region extending in a first direction; a device isolation layer on side surfaces of the active region and defining the active region; a gate structure intersecting the active region on the active region and extending in a second direction; source/drain regions in regions in which the active region is recessed, on both sides of the gate structure; first protective layers between the device isolation layer and the gate structure; and a buried interconnection line below the source/drain regions and connected to one of the source/drain regions through an upper surface of the buried interconnection line.

公开(公告)号：US20220399449A1

公开(公告)日：2022-12-15

申请号：US17679361

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohyun LEE ,  Heonjong SHIN ,  Minchan GWAK

IPC: H01L29/417 ,  H01L29/78 ,  H01L23/522 ,  H01L29/06

Abstract: A semiconductor device includes an active region on a substrate, gate structures intersecting the active region on the substrate, source/drain regions on both sides of the gate structures, a contact structure in a contact hole exposing the source/drain regions, the contact structure comprising a barrier layer and a plug layer, and an insulating pattern in a remaining space of the contact hole, wherein the contact structure includes a first portion filling a lower portion of the contact hole and a second portion protruding from a region of the first portion, the plug layer extends continuously from the first portion to the second portion, and the barrier layer of the second portion has upper ends at a level lower than an upper surface of the plug layer of the second portion on both sides of the plug layer of the second portion.

公开(公告)号：US20220384591A1

公开(公告)日：2022-12-01

申请号：US17546213

申请日：2021-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohyun LEE ,  Heonjong SHIN ,  Seon-Bae KIM ,  Minchan GWAK ,  Jinyoung PARK ,  Hyunho PARK

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device may include an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, a gate electrode on the channel pattern, an active contact on the source/drain pattern, a first lower interconnection line on the gate electrode, and a second lower interconnection line on the active contact and at the same level as the first lower interconnection line. The gate electrode may include an electrode body portion and an electrode protruding portion, wherein the electrode protruding portion protrudes from a top surface of the electrode body portion and is in contact with the first lower interconnection line thereon. The active contact may include a contact body portion and a contact protruding portion, wherein the contact protruding portion protrudes from a top surface of the contact body portion and is in contact with the second lower interconnection line thereon.

公开(公告)号：US20190157406A1

公开(公告)日：2019-05-23

申请号：US16014496

申请日：2018-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inchan HWANG ,  Heonjong SHIN ,  Sunghun JUNG ,  Doohyun LEE ,  Hwichan JUN ,  Hakyoon AHN

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L27/092 ,  H01L21/285 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device is disclosed. The semiconductor device may include a substrate including a first active pattern, the first active pattern vertically protruding from a top surface of the substrate, a first source/drain pattern filling a first recess, which is formed in an upper portion of the first active pattern, a first metal silicide layer on the first source/drain pattern, the first metal silicide layer including a first portion and a second portion, which are located on a first surface of the first source/drain pattern, and a first contact in contact with the second portion of the first metal silicide layer. A thickness of the first portion may be different from a thickness of the second portion.