公开(公告)号：US11798850B2

公开(公告)日：2023-10-24

申请号：US17398623

申请日：2021-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi Chan Jun ,  Chang Hwa Kim ,  Dae Won Ha

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L23/522 ,  H01L21/8238

CPC classification number: H01L21/823475 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823814 ,  H01L21/823878

Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.

公开(公告)号：US11309405B2

公开(公告)日：2022-04-19

申请号：US16846813

申请日：2020-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi Chan Jun ,  Min Gyu Kim ,  Seon Bae Kim

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8234

Abstract: A method for manufacturing a vertical field effect transistor (VFET) device may include: providing an intermediate VFET structure including a substrate, a plurality of fin structures formed thereon, and a doped layer formed on the substrate between the fin structures, the doped layer comprising a bottom source/drain (S/D) region; forming a shallow trench through the doped layer and the substrate below a top surface of the substrate and between the fin structures, to isolate the fin structures from each other; filling the shallow trench and a space between the fin structures with an insulating material; etching the insulating material filled between the fin structures above a level of a top surface of the doped layer, except in the shallow trench, such that a shallow trench isolation (STI) structure having a top surface to be at or above a level of the top surface of the doped layer is formed in the shallow trench; forming a plurality of gate structures on the fin structures, respectively; and forming a top S/D region above the fin structures.

公开(公告)号：US20210242025A1

公开(公告)日：2021-08-05

申请号：US17026532

申请日：2020-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Gyu Kim ,  Hwi Chan Jun

IPC: H01L21/285 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

Abstract: A vertical field effect transistor (VFET) structure includes: a substrate; fin structures formed on the substrate; bottom source/drain regions formed on the substrate between and at opposite sides of lower portions of the fin structures; and shallow trench isolation (STI) structures formed at sides of the substrate and the bottom source/drain regions, wherein upper portions of the bottom source/drain regions include silicide layers each of which has a bar shape.

公开(公告)号：US10553484B2

公开(公告)日：2020-02-04

申请号：US15959783

申请日：2018-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Chan Gwak ,  Hwi Chan Jun ,  Heon Jong Shin ,  So Ra You ,  Sang Hyun Lee ,  In Chan Hwang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a plurality of active regions spaced apart from each other and extending linearly in parallel on a substrate. A gate electrode crosses the plurality of active regions, and respective drain regions are on and/or in respective ones of the active regions on a first side of the gate electrode and respective source regions are on and/or in respective ones of the active regions on a second side of the gate electrode. A drain plug is disposed on the drain regions and a source plug is disposed on the source regions. A gate plug is disposed on the gate electrode between the drain plug and the source plug such that a straight line passing through a center of the drain plug and a center of the source plug intersects the gate plug.

公开(公告)号：US11804540B2

公开(公告)日：2023-10-31

申请号：US18071168

申请日：2022-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi Chan Jun ,  Min Gyu Kim ,  Gil-Hwan Son

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/285

CPC classification number: H01L29/66666 ,  H01L21/28512 ,  H01L29/41741 ,  H01L29/7827

Abstract: A vertical field effect transistor (VFET) device and a method of manufacturing the same are provided. The method includes: (a) providing an intermediate VFET structure comprising a substrate, and fin structures, gate structures and bottom epitaxial layers on the substrate, the gate structures being formed on the fin structures, respectively, each fin structure comprising a fin and a mask thereon, and the bottom epitaxial layers; (b) filling interlayer dielectric (ILD) layers between and at sides of the gate structures; (c) forming an ILD protection layer on the ILD layers, respectively, the ILD protection layer having upper portions and lower portions, and comprising a material preventing oxide loss at the ILD layers; (d) removing the fin structures, the gate structures and the ILD protection layer above the lower portion of the ILD protection layer; (e) removing the masks of the fin structures and top portions of the gate structures so that top surfaces of the fin structures and top surfaces of the gate structures after the removing are lower than top surfaces of the ILD layers; (f) forming top spacers on the gate structures of which the top portions are removed, and top epitaxial layers on the fin structures of which the masks are removed; and (g) forming a contact structure connected to the top epitaxial layers.

公开(公告)号：US11322602B2

公开(公告)日：2022-05-03

申请号：US16794358

申请日：2020-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwi Chan Jun ,  Kang-Ill Seo ,  Jeong Hyuk Yim

IPC: H01L29/66 ,  H01L29/78

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a preliminary VFET on a substrate. The preliminary VFET may include a bottom source/drain region on the substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, a patterned sacrificial layer on a side surface of the channel region, and an insulating layer. The top source/drain region and the patterned sacrificial layer may be enclosed by the insulating layer. The methods may also include forming a contact opening extending through the insulating layer and exposing a portion of the patterned sacrificial layer, forming a cavity between the channel region and the insulating layer by removing the patterned sacrificial layer through the contact opening, and forming a gate electrode in the cavity.

公开(公告)号：US11282752B2

公开(公告)日：2022-03-22

申请号：US17035857

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwi Chan Jun ,  Min Gyu Kim

IPC: H01L21/8234

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the same are provided. The methods may include forming a lower structure on a substrate. The lower structure may include first and second VFETs, a preliminary isolation structure between the first and second VFETs, and a gate liner on opposing sides of the preliminary isolation structure and between the preliminary isolation structure and the substrate. Each of the first and second VFETs may include a bottom source/drain region, a channel region and a top source/drain region sequentially stacked, and a gate structure on a side surface of the channel region. The preliminary isolation structure may include a sacrificial layer and a gap capping layer sequentially stacked. The methods may also include forming a top capping layer on the lower structure and then forming a cavity between the first and second VFETs by removing the sacrificial layer.

公开(公告)号：US10818549B2

公开(公告)日：2020-10-27

申请号：US16724483

申请日：2019-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Chan Gwak ,  Hwi Chan Jun ,  Heon Jong Shin ,  So Ra You ,  Sang Hyun Lee ,  In Chan Hwang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L29/775

Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.

公开(公告)号：US10658288B2

公开(公告)日：2020-05-19

申请号：US16420825

申请日：2019-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seul Ki Hong ,  Heon Jong Shin ,  Hwi Chan Jun ,  Min Chan Gwak

IPC: H01L23/522 ,  H01L29/78 ,  H01L27/088 ,  H01L23/532 ,  H01L23/535 ,  H01L29/06 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/321 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/417 ,  H01L21/768 ,  H01L23/485 ,  H01L27/12 ,  H01L21/84

Abstract: A semiconductor device includes a substrate having a device isolation region defining an active region. An active fin is positioned in the active region. A gate structure overlaps the active fin along a direction orthogonal to an upper surface of the substrate and extends in a second direction intersecting the first direction. A source/drain region is disposed on the active fin. A contact plug is connected to the source/drain region and overlaps the active fin. A metal via is positioned at a first level above the substrate higher than an upper surface of the contact plug and spaced apart from the active fin. A metal line is positioned at a second level above the substrate, higher than the first level and connected to the metal via. A via connection layer extends from an upper portion of the contact plug and is connected to the metal via.