公开(公告)号：US20230411259A1

公开(公告)日：2023-12-21

申请号：US18110994

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunchul Kim ,  Junwoo Park ,  Hyunggil Baek ,  Yongkwan Lee ,  Juhyung Lee

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L23/49833 ,  H01L24/16 ,  H01L23/3128 ,  H01L2224/16227 ,  H01L23/49822

Abstract: A semiconductor package includes: a lower substrate; a semiconductor chip disposed on the lower substrate; an upper substrate disposed on the semiconductor chip, having a lower surface facing the semiconductor chip, and including step structures disposed below the lower surface; a connection structure disposed around the semiconductor chip and connecting the lower substrate to the upper substrate; and an encapsulant filling a space between the lower substrate and the upper substrate and sealing at least a portion of each of the semiconductor chip and the connection structure. The lower surface of the upper substrate has a first surface portion on which the step structures are disposed and a second surface portion having a step with respect to the lower surface of the step structures, and the second surface portion extends between opposite edges of the upper substrate.

公开(公告)号：US20210320042A1

公开(公告)日：2021-10-14

申请号：US17098748

申请日：2020-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Hyunggil Baek ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongho Park ,  Yongkwan Lee

IPC: H01L23/16 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package is provided. The semiconductor package includes: a first package substrate; a first semiconductor chip on the first package substrate; an interposer substrate including a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface of the interposer substrate; a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad; a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with an outer wall of the first dam structure; and a conductive connector in contact with an inner wall of the at least one first dam structure and with the upper conductive pad.

公开(公告)号：US20180261555A1

公开(公告)日：2018-09-13

申请号：US15850336

申请日：2017-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae CHO ,  Sundae KIM ,  Hyunggil Baek ,  Namgyu BAEK ,  Seunghun SHIN ,  Donghoon WON

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/02

Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.