公开(公告)号：US11476257B2

公开(公告)日：2022-10-18

申请号：US17371522

申请日：2021-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhak Lee ,  Seunghun Lee ,  Sangyeop Baeck ,  Seunghan Park ,  Hyejin Lee

IPC: G11C5/06 ,  H01L27/11 ,  G11C11/417 ,  G11C11/412

Abstract: An integrated circuit includes: a first wiring layer on which a first bit line pattern and a positive power supply pattern, a first power supply line landing pad, and a first word line landing pad are formed; a second wiring layer on which a first negative power supply pattern connected to the first power supply line landing pad, and a first word line pattern connected to the first word line landing pad are formed; a third wiring layer on which a second negative power supply pattern connected to the first negative power supply pattern, and a second word line landing pad connected to the first word line pattern are formed; and a fourth wiring layer on which a second word line pattern, connected to the second word line landing pad, are formed.

公开(公告)号：US10885954B2

公开(公告)日：2021-01-05

申请号：US15840601

申请日：2017-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yeop Baeck ,  Inhak Lee ,  SangShin Han ,  Tae-Hyung Kim ,  JaeSeung Choi ,  Sunghyun Park ,  Hyunsu Choi

IPC: G11C7/10 ,  G11C11/419 ,  G11C11/4096 ,  G11C7/12 ,  G11C5/14 ,  G11C8/08 ,  G11C8/16 ,  G11C11/412

Abstract: A memory device includes a first write assist circuit providing a cell voltage or a write assist voltage to a first memory cell connected with a first bit line pair, a first write driver that provides write data to the first memory cell through the first bit line pair, a second write assist circuit that provides the cell voltage or the write assist voltage to a second memory cell connected with a second bit line pair, and a second write driver that provides write data to the second memory cell through the second bit line pair. One of the first and second write assist circuits provides the write assist voltage in response to a column selection signal for selecting one write driver, which provides write data, from among the first, and second write drivers, and the other thereof provides the cell voltage in response to the column selection signal.

公开(公告)号：US10424577B2

公开(公告)日：2019-09-24

申请号：US15842995

申请日：2017-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhak Lee ,  Sang-Yeop Baeck ,  JaeSeung Choi ,  Hyunsu Choi ,  SangShin Han

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/11 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8238 ,  G06F17/50 ,  H01L29/78

Abstract: A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.

公开(公告)号：US10211212B2

公开(公告)日：2019-02-19

申请号：US15701527

申请日：2017-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhak Lee

IPC: H01L27/112 ,  H01L23/522

Abstract: A semiconductor device includes a substrate having a first active region; first and second gate electrodes disposed on the first active region; first, second and third impurity regions disposed in the first active region; first, second and third active contacts disposed on and connected to the first, second and third impurity regions; a first power line electrically connected to the first impurity region through the first active contact; and a first bit line electrically connected to the second and third impurity regions through the second and third active contacts. The first gate electrode and the first and second impurity regions form a first transistor of a first memory cell. The second gate electrode and the second and third impurity regions form a second transistor of a second memory cell. The second impurity region is a drain of the first and second transistors of the first and second memory cells.

公开(公告)号：US20180158516A1

公开(公告)日：2018-06-07

申请号：US15706859

申请日：2017-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： INGYU PARK ,  Inhak Lee ,  Chanho Lee ,  Jaeseung Choi

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1096 ,  G11C11/412 ,  H01L27/1104

Abstract: A static random access memory device includes a plurality of memory cells arranged in rows and columns, a write driver configured to apply a bit line voltage corresponding to write data to a bit line extending in a column direction of the plurality of memory cells in a write operation, and a sub power line configured to transmit a cell driving voltage to the plurality of memory cells in the write operation and to extend in a direction parallel to the bit line, and includes a first node and a second node. The cell driving voltage is applied to the first node of the sub power line and the first node of the sub power line is aligned with an output node of the write driver in a row direction of the plurality of memory cells.

公开(公告)号：US20250167805A1

公开(公告)日：2025-05-22

申请号：US18764731

申请日：2024-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiryong Kim ,  Inhak Lee ,  Jaesung Choi

IPC: H03M13/09 ,  H03M13/00

Abstract: An example column redundancy circuit of a memory device comprises a pre-decoder circuit, a main decoder circuit, and a shift logic circuit. The pre-decoder circuit is configured to receive a lower column address from a plurality of fault column addresses and perform a first decoding operation, and to receive an upper column address from the plurality of fault column address and perform a second decoding operation. The main decoder circuit includes a plurality of main decoders, and each main decoder is configured to receive a lower signal and one or more upper signals from the pre-decoder circuit and to perform a main decoding operation. The shift logic circuit includes a plurality of shift logics, and each shift logic is configured to generate a shift signal that performs a column shift operation according to a result of the main decoding operation.

公开(公告)号：US12300309B2

公开(公告)日：2025-05-13

申请号：US17881187

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmyung Kang ,  Hoyoung Tang ,  Inhak Lee ,  Sangyeop Baeck ,  Dongwook Seo

IPC: G11C16/04 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096

Abstract: A memory device includes a bit cell array including a plurality of bit cells connected to a first auxiliary line to which a cell power voltage is supplied; a write driver configured to apply a bit line voltage corresponding to write data to a bit line extending in a column direction of the bit cell array during a write operation; and a write auxiliary circuit connected to the first auxiliary line and a second auxiliary line extending in parallel to the first auxiliary line, and configured to lower a cell power voltage for a first bit cell spaced apart from the write driver during the write operation, wherein the cell power voltage is supplied to the first auxiliary line through the second auxiliary line, and in sequence from the first bit cell to a second bit cell adjacent to the write driver through the first auxiliary line.

公开(公告)号：US11875844B2

公开(公告)日：2024-01-16

申请号：US17577198

申请日：2022-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inhak Lee ,  Sang-Yeop Baeck ,  Younghwan Park ,  Jaesung Choi

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/418

Abstract: Disclosed is a static random access memory (SRAM) device. According to example embodiments of the present disclosure, a control logic of the SRAM device may include a tracking circuit connected with metal lines for tracking the number of columns of a memory cell array and the number of rows of the memory cell array. By the tracking circuit, a length of word lines of the memory cell array and a length of bit lines of the memory cell array may be tracked. The control logic of the SRAM device may generate control pulses optimized for the size of the memory cell array, based on a tracking result(s) of the tracking circuit. Accordingly, a power and a time necessary for a write operation and a read operation may be reduced.

公开(公告)号：US11183233B2

公开(公告)日：2021-11-23

申请号：US16566002

申请日：2019-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop Baeck ,  Tae-Hyung Kim ,  Daeyoung Moon ,  Dong-Wook Seo ,  Inhak Lee ,  Hyunsu Choi ,  Taejoong Song ,  Jae-Seung Choi ,  Jung-Myung Kang ,  Hoon Kim ,  Jisu Yu ,  Sun-Yung Jang

IPC: G11C11/419 ,  G11C7/08 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US11127730B2

公开(公告)日：2021-09-21

申请号：US16539474

申请日：2019-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhak Lee ,  Sang-Yeop Baeck ,  JaeSeung Choi ,  Hyunsu Choi ,  SangShin Han

IPC: H01L27/02 ,  H01L23/528 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/11 ,  H01L27/092 ,  G06F30/398 ,  H01L29/78 ,  G06F30/392 ,  G06F30/394

Abstract: A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.