公开(公告)号：US20190326180A1

公开(公告)日：2019-10-24

申请号：US16460127

申请日：2019-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hyun LEE ,  Jeong Yun LEE ,  Seung Ju PARK ,  Geum Jung SEONG ,  Young Mook OH ,  Seung Soo HONG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction. The semiconductor device includes a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer; a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction.

公开(公告)号：US20190288065A1

公开(公告)日：2019-09-19

申请号：US15992401

申请日：2018-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namkyu Edward CHO ,  Seung Soo HONG ,  Geum Jung SEONG ,  Seung Hun LEE ,  Jeong Yun LEE

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/306 ,  H01L27/11 ,  H01L21/02 ,  H01L29/165 ,  H01L29/78

Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.

公开(公告)号：US20180158836A1

公开(公告)日：2018-06-07

申请号：US15869599

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo Soon KIM ,  Hyun Ji KIM ,  Jeong Yun LEE ,  Gi Gwan PARK ,  Sang Duk PARK ,  Young Mook OH ,  Yong Seok LEE

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/7853

Abstract: There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure. The semiconductor device includes a substrate including a first region and a second region, a first wire pattern provided on the first region of the substrate and spaced apart from the substrate, a second wire pattern provided on the second region of the substrate and spaced apart from the substrate, a first gate insulating film surrounding a perimeter of the first wire pattern, a second gate insulating film surrounding a perimeter of the second wire pattern, a first gate electrode provided on the first gate insulating film, intersecting with the first wire pattern, and including a first metal oxide film therein, a second gate electrode provided on the second gate insulating film and intersecting with the second wire pattern, a first gate spacer on a sidewall of the first gate electrode, and a second gate spacer on a sidewall of the second gate electrode.

公开(公告)号：US20180138092A1

公开(公告)日：2018-05-17

申请号：US15718482

申请日：2017-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hyun LEE ,  Jeong Yun LEE ,  Seung Ju PARK ,  Geum Jung SEONG ,  Young Mook OH ,  Seung Soo HONG

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L21/823462 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/6656 ,  H01L29/785

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction. The semiconductor device includes a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer; a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction.