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    Digital-analog conversion apparatus and method
    11.
    发明授权
    Digital-analog conversion apparatus and method 有权
    数模转换装置及方法

    公开(公告)号：US08760332B2

    公开(公告)日：2014-06-24

    申请号：US13705550

    申请日：2012-12-05

    Applicant: Samsung Electronics Co. Ltd.

    Inventor： Jong-Woo Lee

    IPC: H03M1/66

    CPC classification number: H03M1/1071 ,  G06F11/0751 ,  H03M1/0651 ,  H03M1/1019 ,  H03M1/66 ,  H03M1/682 ,  H03M1/687 ,  H03M1/747

    Abstract: An apparatus and a method for digital-analog conversion are provided. The apparatus includes a first cell matrix for outputting a current of a signal corresponding to a number of Most Significant Bits (MSBs) of an input digital signal, a second cell matrix for outputting a current of a signal corresponding to a number of Least Significant Bits (LSBs) of the input digital signal, an amplifier for amplifying the output current of the second cell matrix at a preset amplification, and an adder for adding the output current of the first cell matrix and the output current of the amplifier.

    Abstract translation: 提供了一种用于数模转换的装置和方法。 该装置包括用于输出与输入数字信号的最高有效位数（MSB）相对应的信号的电流的第一单元矩阵，用于输出与多个最低有效位相对应的信号的电流的第二单元矩阵 （LSB），用于以预设放大放大第二单元矩阵的输出电流的放大器，以及用于将第一单元矩阵的输出电流和放大器的输出电流相加的加法器。

    Voltage controlled oscillator using variable capacitor and phase locked loop using the same
    14.
    发明授权
    Voltage controlled oscillator using variable capacitor and phase locked loop using the same 有权

    公开(公告)号：US10516404B2

    公开(公告)日：2019-12-24

    申请号：US15923620

    申请日：2018-03-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-Woo Lee

    IPC: H03B5/12 ,  H03C3/09 ,  H03L7/099 ,  H01G15/00

    Abstract: A variable capacitor is provided. The variable capacitor includes a plurality of capacitor segments. The plurality of capacitor segments are connected in parallel within the variable capacitor. When a plurality of candidate capacitances allowable to the variable capacitor according to a connection state of the plurality of capacitor segments connected in parallel are sorted in a magnitude sequence, the plurality of candidate capacitances form a geometric series. The variable capacitor is used for a Voltage Controlled Oscillator (VCO), and the VCO is used for a Phase Locked Loop (PLL).

    CARRIER AGGREGATED SIGNAL TRANSMISSION AND RECEPTION
    15.
    发明申请
    CARRIER AGGREGATED SIGNAL TRANSMISSION AND RECEPTION 审中-公开

    公开(公告)号：US20190173501A1

    公开(公告)日：2019-06-06

    申请号：US16203943

    申请日：2018-11-29

    Applicant: Samsung Electronics Co., LTD.

    Inventor： SEUNG-HYUN OH ,  Chilun Lo ,  Barosaim Sung ,  Jae-Hoon Lee ,  Jong-Woo Lee

    IPC: H04B1/00 ,  H04L27/26 ,  H03L7/08

    Abstract: Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively, Each of the first and second carrier receivers may further include a digital mixer for farther translating the frequencies of the receive signal in the digital domain.

    Apparatus and method for detecting phase lock in an electronic device
    16.
    发明授权
    Apparatus and method for detecting phase lock in an electronic device 有权

    公开(公告)号：US10031169B2

    公开(公告)日：2018-07-24

    申请号：US15004497

    申请日：2016-01-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Manthena Vamshi ,  Jong-Woo Lee ,  Thomas Byunghak Cho ,  Byung-Ki Han

    IPC: G01R25/00 ,  H03L7/095

    Abstract: The present disclosure provides a method and a phase lock detection apparatus for detecting whether a phase of an output signal is locked to the phase of a reference signal. The apparatus includes a first divider that individually frequency-divides first and second pulse signals, a phase frequency detector that outputs third and fourth pulse signals that correspond to a phase difference between the frequency-divided first and second pulse signals, a second divider that individually frequency-divides the third and fourth pulse signals, and a determiner that determines whether a phase of the second pulse signal is locked, based on the frequency-divided third and fourth pulse signals.

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