公开(公告)号：US10109642B2

公开(公告)日：2018-10-23

申请号：US15275972

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/792 ,  H01L27/105 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/306 ,  H01L21/3213 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/45 ,  H01L27/1158

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

公开(公告)号：US09070581B2

公开(公告)日：2015-06-30

申请号：US14083971

申请日：2013-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC: H01L21/336 ,  H01L27/105 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/11582 ,  H01L21/02524 ,  H01L21/02587 ,  H01L21/02598 ,  H01L21/02675 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/32133 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1158 ,  H01L29/4234 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

Abstract translation: 在垂直型存储器件和垂直型存储器件的制造方法中，垂直存储器件包括设置在衬底上的线状绝缘层图形，柱状单晶半导体图案设置在两侧壁上 设置在每个单晶半导体图案的侧壁上的绝缘层图案和晶体管。 晶体管沿着单晶半导体图案的垂直方向排列，因此存储器件可以高度集成。

公开(公告)号：US08603878B2

公开(公告)日：2013-12-10

申请号：US13673396

申请日：2012-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC: H01L21/336

CPC classification number: H01L27/11582 ,  H01L21/02524 ,  H01L21/02587 ,  H01L21/02598 ,  H01L21/02675 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/32133 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1158 ,  H01L29/4234 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

公开(公告)号：US20130049225A1

公开(公告)日：2013-02-28

申请号：US13660177

申请日：2012-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pil-kyu KANG ,  Jung-Ho Kim ,  Jong-Wook Lee ,  Seung-woo Choi ,  Dae-Lok Bae

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/25 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.

Abstract translation: 微电子封装通过彼此堆叠集成电路制造。 每个集成电路包括具有微电子器件的半导体层和在半导体层上具有有选择性地互连微电子器件的布线的布线层。 在堆叠之后，形成延伸通过彼此堆叠的至少两个集成电路的通孔。 然后，通孔被选择性地电接触布线的导电材料填充。 还描述了相关微电子封装。