公开(公告)号：US20170094723A1

公开(公告)日：2017-03-30

申请号：US15275551

申请日：2016-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se Yun KIM ,  Jong Wook ROH ,  Jongmin LEE ,  Doh Won JUNG ,  Sungwoo HWANG ,  Chan KWAK ,  Jinyoung HWANG

IPC: H05B3/12 ,  C01G23/04 ,  C01G55/00 ,  H01B1/02 ,  B22F1/00

Abstract: An electrical conductor including: a first conductive layer including a plurality of metal nanowires; and a second conductive layer disposed on a surface of the first conductive layer, wherein the second conductive layer includes a plurality of metal oxide nanosheets, wherein in the first conductive layer, a metal nanowire of the plurality of metal nanowires contacts at least two metal oxide nanosheets of the plurality of metal oxide nanosheets, and wherein the plurality of metal oxide nanosheets includes an electrical connection between contacting metal oxide nanosheets.

公开(公告)号：US20170092387A1

公开(公告)日：2017-03-30

申请号：US15275538

申请日：2016-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se Yun KIM ,  Jong Wook ROH ,  Woojin LEE ,  Jongmin LEE ,  Doh Won JUNG ,  Sungwoo HWANG ,  Chan KWAK

IPC: H01B1/08 ,  H01B1/16 ,  H01B5/14 ,  H01B13/00

CPC classification number: H01B1/08 ,  G06F3/041 ,  G06F2203/04102 ,  G06F2203/04103 ,  H01B1/00 ,  H01B1/16 ,  H01B5/14 ,  H01B13/0036

Abstract: An electrical conductor including a first conductive layer including a plurality of ruthenium oxide nanosheets, wherein the plurality of ruthenium oxide nanosheets include an electrical connection between contacting ruthenium oxide nanosheets and at least one of the plurality of ruthenium oxide nanosheets includes a plurality of metal clusters on a surface of the at least one ruthenium oxide nanosheet.

公开(公告)号：US20170064822A1

公开(公告)日：2017-03-02

申请号：US15235363

申请日：2016-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doh Won JUNG ,  Yoon Chul SON ,  Woojin LEE ,  Jongmin LEE

IPC: H05K1/09 ,  H05K3/22

CPC classification number: H05K1/09 ,  H05K1/028 ,  H05K1/0393 ,  H05K3/22 ,  H05K3/24 ,  H05K2201/0326 ,  H05K2201/0338 ,  H05K2203/0108 ,  H05K2203/0257 ,  H05K2203/1105

Abstract: An electrical conductor includes a first conductive layer including a plurality of metal oxide nanosheets, wherein a metal oxide nanosheet of the plurality of metal oxide nanosheets includes a proton bonded to a the surface of the metal oxide nanosheet, wherein the metal oxide is represented by Chemical Formula 1: MO2   Chemical Formula 1 wherein M is Re, V, Os, Ru, Ta, Ir, Nb, W, Ga, Mo, In, Cr, Rh, or Mn, wherein the plurality of metal oxide nanosheets has a content of hydrogen atoms of less than about 100 atomic percent, with respect to 100 atomic percent of metal atoms as measured by Rutherford backscattering spectrometry, and wherein the plurality of metal oxide nanosheets includes an electrical connection between contacting metal oxide nanosheets.

Abstract translation: 其中M是Re，V，Os，Ru，Ta，Ir，Nb，W，Ga，Mo，In，Cr，Rh或Mn，其中多个金属氧化物纳米片的氢原子含量小于约100 原子百分比，相对于通过卢瑟福背散射光谱法测量的100原子％的金属原子，并且其中多个金属氧化物纳米片包括在接触金属氧化物纳米片之间的电连接。

公开(公告)号：US20250062193A1

公开(公告)日：2025-02-20

申请号：US18934456

申请日：2024-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil LEE ,  Jongmin LEE ,  Jimin CHOI ,  Yeonjin LEE

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535

Abstract: A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.

公开(公告)号：US20240153919A1

公开(公告)日：2024-05-09

申请号：US18451197

申请日：2023-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong KIM ,  Jongmin LEE ,  Jimin CHOI

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3142 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/08113 ,  H01L2224/0903 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor package includes a first semiconductor chip including a circuit layer on a first substrate, first through silicon vias passing through the first substrate, first lower bump pads on the circuit layer, and a first upper bump pad and a second upper bump pad on a second surface of the first substrate, each of the first upper bump pad and the second upper bump pad connected to a corresponding one of the first through silicon vias. The package includes a second semiconductor chip including a circuit layer on a first surface of a second substrate, and second lower bump pads on the circuit layer on the second substrate. The package includes a first solder bump to bond the first upper bump pad and the second lower bump pad, and a plurality of second solder bumps to bond the second upper bump pad and the second lower bump pads.

公开(公告)号：US20240038675A1

公开(公告)日：2024-02-01

申请号：US18313491

申请日：2023-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimin CHOI ,  Joongwon SHIN ,  Sungyun WOO ,  Yeonjin LEE ,  Jongmin LEE ,  Sehyun HWANG

IPC: H01L23/544 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L25/18 ,  H10B80/00 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2223/54426

Abstract: A semiconductor device may include a plurality of chip regions on a substrate, at least one scribe lane surrounding each of the plurality of chip regions on the substrate, a plurality of first align key patterns and a plurality of first test element group patterns included in the plurality of chip regions, and a plurality of second align key patterns and a plurality of second test element group patterns included in the at least one scribe lane.

公开(公告)号：US20230187844A1

公开(公告)日：2023-06-15

申请号：US18078356

申请日：2022-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongmin LEE ,  Seungtae KO ,  Yoongeon KIM ,  Sanghoon PARK ,  Jungmin PARK ,  Bumhee LEE ,  Seokmin LEE ,  Seungho CHOI

IPC: H01Q21/06 ,  H01Q25/00

CPC classification number: H01Q21/065 ,  H01Q25/001

Abstract: The present disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting a higher data transmission rate after a 4th generation (4G) communication system such as long-term evolution (LTE). An antenna in a wireless communication system may include: a plurality of antenna elements including a first antenna element and a second antenna element, the first antenna element and the second antenna element may include patch antennas, the first antenna element and the second antenna element may be disposed at a narrower interval than a reference interval, and the patch antenna may have an asymmetry structure.

公开(公告)号：US20230116911A1

公开(公告)日：2023-04-13

申请号：US17736212

申请日：2022-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil LEE ,  Jongmin LEE ,  Jimin CHOI ,  Yeonjin LEE

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768

Abstract: A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.

公开(公告)号：US20230077803A1

公开(公告)日：2023-03-16

申请号：US17751740

申请日：2022-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jimin CHOI ,  Jongmin LEE ,  Yeonjin LEE ,  Jeonil LEE ,  Juik LEE ,  Minjung CHOI

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor device includes a substrate, an etch stop layer on the substrate, a through-hole electrode extending through the substrate and the etch stop layer in a vertical direction substantially perpendicular to an upper surface of the substrate, and a conductive pad. The etch stop layer includes a first surface adjacent to the substrate and a second surface opposite the first surface. The through-hole electrode includes a protrusion portion that protrudes from the second surface of the etch stop layer. The conductive pad covers the protrusion portion of the through-hole electrode. The protrusion portion of the through-hole electrode is not flat.

公开(公告)号：US20230005818A1

公开(公告)日：2023-01-05

申请号：US17574902

申请日：2022-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonjin LEE ,  Jongmin LEE ,  Jeonil LEE

IPC: H01L23/48 ,  H01L27/105 ,  H01L21/768 ,  H01L25/065

Abstract: A semiconductor device according to some example embodiments includes a substrate, an insulating structure covering the substrate, a transistor between the substrate and the insulating structure, a via insulating layer extending through the insulating structure and the substrate, a plurality of via structures extending through the via insulating layer, a plurality of conductive structures respectively connected to the plurality of via structures, and a plurality of bumps respectively connected to the conductive structures.