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    METHOD OF OPERATING DATA COMPRESSION CIRCUIT AND DEVICES TO PERFORM THE SAME
    11.
    发明申请
    METHOD OF OPERATING DATA COMPRESSION CIRCUIT AND DEVICES TO PERFORM THE SAME 有权
    操作数据压缩电路的方法和执行相同的设备

    公开(公告)号：US20140195702A1

    公开(公告)日：2014-07-10

    申请号：US14146846

    申请日：2014-01-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD

    Inventor： Man Keun SEO ,  Dae Wook KIM ,  Hong Rak SON ,  Jun Jin KONG

    IPC: G06F5/14

    CPC classification number: H03M7/30 ,  G06F13/14 ,  G06F13/1668 ,  H03M7/3084 ,  H03M7/3091

    Abstract: A method of operating a data compression circuit includes receiving and storing a plurality of data blocks until a cache is full and writing the data blocks that have been stored in the cache to a buffer memory when the cache is full. The method also includes performing forced literal/literal encoding on each of the data blocks regardless of repetitiveness of each data block when the cache is full.

    Abstract translation: 一种操作数据压缩电路的方法包括接收和存储多个数据块，直到高速缓存满了，并且当高速缓存已满时将已经存储在高速缓存中的数据块写入缓冲存储器。 该方法还包括对每个数据块执行强制文字/文字编码，而不管每个数据块在高速缓存满时的重复性。

    SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, AND MEMORY SYSTEM
    15.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, AND MEMORY SYSTEM 审中-公开

    公开(公告)号：US20200133768A1

    公开(公告)日：2020-04-30

    申请号：US16372047

    申请日：2019-04-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myung Kyu LEE ,  Jun Jin KONG ,  Ki Jun LEE ,  Sung Hye CHO ,  Dae Hyun KIM ,  Yong Gyu CHU

    IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29

    Abstract: Disclosed are a semiconductor memory device, a controller, and a memory system. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

    MEMORY SYSTEM ARCHITECTURE INCLUDING SEMI-NETWORK TOPOLOGY WITH SHARED OUTPUT CHANNELS
    17.
    发明申请
    MEMORY SYSTEM ARCHITECTURE INCLUDING SEMI-NETWORK TOPOLOGY WITH SHARED OUTPUT CHANNELS 审中-公开
    存储系统架构，包括具有共享输出通道的半网络拓扑

    公开(公告)号：US20170017590A1

    公开(公告)日：2017-01-19

    申请号：US14801241

    申请日：2015-07-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Amit BERMAN ,  Uri BEITLER ,  Jun Jin KONG

    IPC: G06F13/28 ,  G06F3/06

    CPC classification number: G06F13/28 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0688

    Abstract: A memory system includes a first plurality of nonvolatile memory devices of a first channel of the memory system, the first plurality of memory devices each being connected to a first communications bus; a second plurality of nonvolatile memory devices of a second channel of the memory system, the second plurality of memory devices each being connected to a second communications bus, and a first interconnection between a first memory device and a second memory device, the first memory device being a memory device from among the first plurality of nonvolatile memory devices, the second memory device being a memory device from among the second plurality of nonvolatile memory devices.

    Abstract translation: 存储器系统包括存储器系统的第一通道的第一多个非易失性存储器件，每个第一多个存储器件连接到第一通信总线; 所述存储器系统的第二通道的第二多个非易失性存储器件，所述第二多个存储器件各自连接到第二通信总线，以及第一存储器件和第二存储器件之间的第一互连，所述第一存储器件 作为来自第一多个非易失性存储器件的存储器件，第二存储器件是第二多个非易失性存储器件中的存储器件。

    NON-VOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND STORAGE DEVICE HAVING THE SAME
    18.
    发明申请
    NON-VOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND STORAGE DEVICE HAVING THE SAME 有权

    公开(公告)号：US20220172786A1

    公开(公告)日：2022-06-02

    申请号：US17675085

    申请日：2022-02-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong Jin SHIN ,  Ji Su KIM ,  Dae Seok BYEON ,  Ji Sang LEE ,  Jun Jin KONG ,  Eun Chu OH

    IPC: G11C16/26 ,  G11C16/10 ,  G11C5/14 ,  G11C16/08 ,  G11C16/32 ,  G11C11/56 ,  G11C16/24

    Abstract: A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.

    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
    19.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20210303395A1

    公开(公告)日：2021-09-30

    申请号：US17344180

    申请日：2021-06-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dae-Hyun KIM ,  Yong-Gyu CHU ,  Jun Jin KONG ,  Ki-Jun LEE ,  Myung-Kyu LEE

    IPC: G06F11/10 ,  G11C29/52 ,  G06F13/16 ,  G11C11/401 ,  H01L25/065

    Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.

    NON-VOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND STORAGE DEVICE HAVING THE SAME
    20.
    发明申请
    NON-VOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND STORAGE DEVICE HAVING THE SAME 有权

    公开(公告)号：US20210005271A1

    公开(公告)日：2021-01-07

    申请号：US17029265

    申请日：2020-09-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong Jin SHIN ,  Ji Su KIM ,  Dae Seok BYEON ,  Ji Sang LEE ,  Jun Jin KONG ,  Eun Chu OH

    IPC: G11C16/26 ,  G11C16/10 ,  G11C5/14 ,  G11C16/24 ,  G11C16/08 ,  G11C16/32 ,  G11C11/56

    Abstract: A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.

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