公开(公告)号：US20250076963A1

公开(公告)日：2025-03-06

申请号：US18953903

申请日：2024-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungchul JEON ,  Jae Min KIM ,  Hyunseok KIM ,  Junho HUH

IPC: G06F1/3287 ,  G06F1/3296 ,  H03K17/687

Abstract: A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.

公开(公告)号：US20250062691A1

公开(公告)日：2025-02-20

申请号：US18635635

申请日：2024-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungchul JEON ,  Junho HUH

IPC: H02M3/158

Abstract: Provided is a switching voltage regulator including: a converting circuit configured to receive an input voltage and to generate an output voltage through a switching operation; and a control circuit configured to cause the output voltage to be generated by controlling the switching operation, wherein the converting circuit includes: at least one switch formed on a first die and configured to perform the switching operation under control of the control circuit; and at least one blocking transistor formed on a second die and electrically connected to at least one first transistor, and wherein the first die is vertically stacked on the second die.

公开(公告)号：US20220309394A1

公开(公告)日：2022-09-29

申请号：US17604202

申请日：2021-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho HUH ,  Hosun LEE ,  Choonghoon LEE

IPC: G06N20/00 ,  G06K9/62

Abstract: An electronic device for collecting training data for generating an artificial intelligence (AI) model is provided. The electronic device includes a communication interface, a memory storing one or more instructions, and a processor configured to execute the one or more instructions stored in the memory. The processor is configured to execute the one or more instructions to obtain first data and characteristic information of the first data, control the communication interface to transmit a data request to an external device and receive characteristic information of second data from the external device, control the communication interface to receive the second data from the external device, based on the characteristic information of the first data and the characteristic information of the second data, determine training data including at least a portion of the first data and at least a portion of the second data, and generate the AI model, based on the determined training data.

公开(公告)号：US20210036596A1

公开(公告)日：2021-02-04

申请号：US15931798

申请日：2020-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungchul JEON ,  Hyunseok KIM ,  Junho HUH ,  Jaemin KIM

IPC: H02M1/00

Abstract: An electronic system includes a plurality of voltage regulators configured to convert an input voltage, a plurality of inductors respectively connected to the plurality of voltage regulators to respectively output a plurality of converting currents, and a switching unit configured to select at least one converting current from among the plurality of converting currents in response to a switching control signal and supply power to a load unit based on the selected at least one converting current.

公开(公告)号：US20250132775A1

公开(公告)日：2025-04-24

申请号：US18768569

申请日：2024-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook HAN ,  Kyoungmin LEE ,  Kyungsoo LEE ,  Junho HUH

IPC: H04B1/00 ,  H03F3/19

Abstract: A radio frequency integrated circuit (RFIC) includes a first receive chain configured to receive a first high-frequency input signal, generate a first baseband signal based on the first high-frequency input signal by using a first downward frequency signal, and output the first baseband signal to a first output port, a first local oscillator configured to generate a first oscillation clock signal, a second local oscillator configured to generate a second oscillation clock signal, a first multiplexer configured to output one among the first and oscillation clock signals to a second output port based on an oscillation clock output selection signal, a first input port configured to receive a third oscillation clock signal from an external source, and a second multiplexer configured to output one among the first through third oscillation signals to the first receive chain as the first downward frequency signal based on a first downward frequency selection signal.

公开(公告)号：US20240234254A9

公开(公告)日：2024-07-11

申请号：US18456865

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongwee YU ,  Junho HUH

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06541 ,  H01L2924/381

Abstract: An integrated circuit device including a first semiconductor chip, a plurality of signal through silicon vias (TSV), a second semiconductor chip, a plurality of signal bumps and an interposer may be provided. The signal TSVs may be in the first semiconductor chip by a first pitch. The second semiconductor chip may be on the first semiconductor chip. The signal bumps may be on a lower surface of the second semiconductor chip by a second pitch wider than the first pitch. The interposer may be interposed between the first semiconductor chip and the second semiconductor chip and may be electrically connecting the signal TSVs with the signal bumps. Thus, an occupying area of the signal TSVs in the first semiconductor chip may be decreased so that the integrated circuit device may have a smaller size.

公开(公告)号：US20240096714A1

公开(公告)日：2024-03-21

申请号：US18462067

申请日：2023-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsoo LEE ,  Junho HUH

IPC: H01L21/66 ,  H01L21/56 ,  H01L23/528 ,  H10B20/25

CPC classification number: H01L22/22 ,  H01L21/56 ,  H01L23/528 ,  H10B20/25

Abstract: Provided are a semiconductor chip and a method of manufacturing a semiconductor package including the semiconductor chip. The semiconductor chip includes a front end of line (FEOL) including an active layer, a back end of line (BEOL) including a plurality of metal layers including a wire, an optional dicing line along which dicing is optionally performed, and an isolation block configured to process a signal for a discontinuous wire when the wire is discontinuous by being diced along the optional dicing line, and a chip die on which the active layer is not formed around a cross section cut by the optional dicing line. Thus, the production yield of the semiconductor chip may be improved, and the production costs thereof may be reduced.

公开(公告)号：US20240029624A1

公开(公告)日：2024-01-25

申请号：US18209540

申请日：2023-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changju LEE ,  Sooyong KIM ,  Taesung KIM ,  Junho HUH

IPC: G09G3/20 ,  G09G3/3233

CPC classification number: G09G3/2096 ,  G09G3/3233 ,  G09G2300/0842 ,  G09G2310/08 ,  G09G2370/00 ,  G09G2300/0861 ,  G09G2320/0247 ,  G09G2330/023

Abstract: A display driving circuit for receiving image data from a host and driving a display panel, the display driving circuit including: an interface configured to receive the image data from the host; and a timing controller configured to control a first interrupt signal for waking up the host in a low-power mode and to control a second interrupt signal based on a light emission control signal, wherein the light emission control signal is for controlling a light emission time of a pixel included in the display panel, and wherein the timing controller is further configured to control a level of the second interrupt signal based on whether the image data has started to be received from the host in response to the first interrupt signal and the second interrupt signal.

公开(公告)号：US20210174813A1

公开(公告)日：2021-06-10

申请号：US17052736

申请日：2019-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junho HUH ,  Hyoungshik KIM ,  Muhammad Ejaz AHMED ,  Ilyoup KWAK ,  Iljoo KIM ,  Sangjoon JE

IPC: G10L17/22 ,  G10L17/06 ,  G10L17/02 ,  G10L17/04 ,  G10L25/21 ,  G06F21/32 ,  G06F21/45

Abstract: Provided are a method of authenticating a voice input provided from a user and a method of detecting a voice input having a strong attack tendency. The voice input authentication method includes: receiving the voice input; obtaining, from the voice input, signal characteristic data representing signal characteristics of the voice input; and authenticating the voice input by applying the obtained signal characteristic data to a first learning model configured to determine an attribute of the voice input, wherein the first learning model is trained to determine the attribute of the voice input based on a voice uttered by a person and a voice output by an apparatus.

公开(公告)号：US20200082101A1

公开(公告)日：2020-03-12

申请号：US16357841

申请日：2019-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Min KIM ,  Jae Won LEE ,  Junho HUH

IPC: G06F21/60 ,  G06F16/182 ,  H04L9/08 ,  H04L9/06 ,  H04L9/32

Abstract: An electronic system includes a plurality of hardware devices and an authenticated circuit. The authenticated circuit is integrated, as fixed hardware, in the electronic system together with the plurality of hardware devices during a manufacturing process of the electronic system, the authenticated circuit configured to verify system integrity based on a system identification code provided from inside of the electronic system by at least one of the plurality of hardware devices, the system integrity indicating that a combination of the authenticated circuit and the plurality of hardware devices has not been modified since the manufacturing process, the authenticated circuit configured to perform a mining operation to generate a next block, the next block to be linked to a blockchain only in response to the authenticated circuit verifying the system integrity. Indiscriminate mining competition may be prevented or reduced in likelihood of occurrence.