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    SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
    11.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20250036521A1

    公开(公告)日：2025-01-30

    申请号：US18770435

    申请日：2024-07-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myungkyu Lee ,  Seongmuk Kang ,  Jae-Gon Lee ,  Kyomin Sohn ,  Yeonggeol Song ,  Kijun Lee

    IPC: G06F11/10

    Abstract: An example CXL (Compute eXpress Link)-based memory module includes a memory device and a controller. The memory device includes a plurality of volatile memory cells and stores data or reads the stored data. The controller communicates with a host device through a CXL interface and controls the memory device. The controller includes an error correction code (ECC) circuit that generates a first codeword by adding a parity vector generated based on Reed-Solomon encoding to data received from the host device, an error injecting circuit that generates an error symbol and generates a second codeword by injecting the error symbol into at least a portion of the first codeword, and a memory device interface that controls the memory device such that the second codeword where the error symbol is injected is stored in the memory device. The controller determines a number of error symbols to be injected into the second codeword.

    Semiconductor memory device and memory system including the same
    14.
    发明授权
    Semiconductor memory device and memory system including the same 有权

    公开(公告)号：US11947810B2

    公开(公告)日：2024-04-02

    申请号：US17743137

    申请日：2022-05-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungrae Kim ,  Hyeran Kim ,  Myungkyu Lee ,  Chisung Oh ,  Kijun Lee ,  Sunghye Cho ,  Sanguhn Cha

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679

    Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

    Semiconductor memory devices and memory systems
    15.
    发明授权
    Semiconductor memory devices and memory systems 有权

    公开(公告)号：US11860734B2

    公开(公告)日：2024-01-02

    申请号：US17736154

    申请日：2022-05-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Sunghye Cho ,  Yeonggeol Song ,  Kijun Lee ,  Myungkyu Lee

    IPC: G11C29/00 ,  G06F11/10 ,  H03M13/11 ,  G06F11/07

    CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/1048 ,  H03M13/1108

    Abstract: A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine, and a control logic circuit. The on-die ECC engine, based on an ECC, in a write operation, performs an ECC encoding on main data to generate first parity data, selectively replaces a portion of the first parity data with a poison flag to generate second parity data based on a poison mode signal, provides the main data to a normal cell region in a target page of the memory cell array, and provides the first parity data to a parity cell region in the target page or provides the poison flag and the second parity data to the parity cell region. The control logic circuit controls the on-die ECC engine and generates the poison mode signal, based on a command and an address from a memory controller.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    16.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11829614B2

    公开(公告)日：2023-11-28

    申请号：US17842981

    申请日：2022-06-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yeonggeol Song ,  Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Eunae Lee ,  Sunghye Cho

    IPC: G06F3/06 ,  G06F11/10

    CPC classification number: G06F3/0626 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068

    Abstract: A semiconductor memory device includes a buffer die and a plurality of memory dies. An error correction code (ECC) engine in one of the memory dies performs an RS encoding on a main data to generate a parity data and performs a RS decoding, using a parity check matrix, on the main data and the parity data. The parity check matrix includes sub matrixes and each of the sub matrixes corresponds to two different symbols. Each of the sub matrixes includes two identity sub matrixes and two same alpha matrixes, the two identity sub matrixes are disposed in a first diagonal direction of the sub matrix and the two same alpha matrixes are disposed in a second diagonal direction. A number of high-level value elements in a y-th row of the parity check matrix is the same as a number of high-level value elements in a (y+p)-th row.

    Memory device performing refresh operation and method of operating the same
    18.
    发明授权
    Memory device performing refresh operation and method of operating the same 有权

    公开(公告)号：US11631448B1

    公开(公告)日：2023-04-18

    申请号：US17244466

    申请日：2021-04-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eunae Lee ,  Sunghye Cho ,  Kijun Lee ,  Junjin Kong ,  Yeonggeol Song

    IPC: G11C11/406 ,  G06F12/06

    Abstract: A memory device includes a memory cell array, an address manager and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The address manager samples access addresses provided from a memory controller to generate sampling addresses and determines a capture address from among the access addresses, based on a time interval between refresh commands from the memory controller. The refresh controller refreshes target memory cells from among the plurality of memory cells based on one of a maximum access address from among the sampling address and the captured address.

    MEMORY DEVICE AND OPERATING METHOD THEREOF
    19.
    发明申请
    MEMORY DEVICE AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20230037996A1

    公开(公告)日：2023-02-09

    申请号：US17718422

    申请日：2022-04-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Myungkyu Lee ,  Kijun Lee ,  Sunghye Cho

    IPC: H03M13/11 ,  H03M13/15 ,  G11C15/04 ,  G11C17/16

    Abstract: An operating method of a memory device includes storing position information regarding a codeword including an erasure and erasure information including position information regarding the erasure in a memory region, loading the position information regarding the codeword to a row decoder and a column decoder, determining whether a read address corresponding to a read instruction is identical to the position information regarding the codeword including the erasure, in response to the read instruction from a host, transmitting the position information of the erasure to an error correction code (ECC) decoder, when the read address is identical to the position information regarding the codeword including the erasure, and correcting, by the ECC decoder, an error in a codeword received from a memory cell array using the position information regarding the erasure.

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