公开(公告)号：US20200043941A1

公开(公告)日：2020-02-06

申请号：US16508839

申请日：2019-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung KIM ,  Kiseok LEE ,  Keunnam KIM ,  Yoosang HWANG

IPC: H01L27/11578 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device may include a stack structure that includes a plurality of layers vertically stacked on a substrate, and a plurality of gate electrodes that vertically extend to penetrate the stack structure. Each of the plurality of layers may include a plurality of semiconductor patterns that extend in parallel along a first direction, a bit line that is electrically connected to the semiconductor patterns and extends in a second direction intersecting the first direction, a first air gap on the bit line, and a data storage element that is electrically connected to a corresponding one of the semiconductor patterns. The first air gap is interposed between the bit line of a first layer of the plurality of layers and the bit line of a second layer of the plurality of layers.

公开(公告)号：US20200001822A1

公开(公告)日：2020-01-02

申请号：US16487965

申请日：2018-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghoon HAN ,  Kiseok LEE ,  Janghee LEE ,  Sungmin JO ,  Ho YANG ,  Myounghwan LEE

IPC: B60R25/01 ,  B60R25/10 ,  H04W12/00 ,  H04W12/06 ,  H04W4/40

Abstract: The present disclosure relates to a communication technique and system thereof that fuses a 5G communication system with Internet of Things (IoT) technology to support a higher data rate than a 4G system. The present disclosure may be applied to an intelligent service (for example, a smart home, a smart building, a smart city, a smart car or a connected car, a health care, a digital education, a retail, a security and safety related services, etc.) on the basis of 5G communication technology and IoT related technology. The present disclosure relates to a technology for a Sensor Network, a Machine to Machine (M2M), a Machine Type Communication (MTC) and an Internet of Things (IoT). The present disclosure may be utilized in the intelligent service (a smart home, a smart building, a smart city, a smart car or a connected car, a health care, a digital education, a retail, a security and safety related service, etc.) on the basis of the above technology. A key authentication method of an apparatus according to one embodiment of the present invention may comprise the steps of: receiving a signal from a terminal using a plurality of communication modules; determining whether the terminal is within a predetermined distance from the apparatus, on the basis of each signal received via the plurality of communication modules; and changing a control mode of a vehicle on which the apparatus is mounted, on the basis of whether the terminal is within the predetermined distance from the apparatus.

公开(公告)号：US20190221475A1

公开(公告)日：2019-07-18

申请号：US16106266

申请日：2018-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiseok HONG ,  Kiseok LEE ,  Jemin PARK ,  Yoosang HWANG

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/7682 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor device includes an interlayer insulation layer on a semiconductor substrate, a via plug and a wiring line on the via plug, in the interlayer insulation layer, the via plug and the wiring line coupled with each other and forming a stepped structure. The semiconductor device includes a first air-gap region between the interlayer insulation layer and the via plug, and a second air-gap region between the interlayer insulation layer and the wiring line. The first air-gap region and the second air-gap region are not vertically overlapped with each other.

公开(公告)号：US20250040123A1

公开(公告)日：2025-01-30

申请号：US18665984

申请日：2024-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin KIM ,  Seungbo KO ,  Kiseok LEE

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate having an active region, a gate structure on the substrate, the gate structure extending across the active region in a first horizontal direction, bit line structures on bit line trenches extending in a second horizontal direction, intersecting the first horizontal direction, the bit line trenches on an upper surface of the substrate across the gate structure, contact plugs between the bit line structures, landing pad structures on the contact plugs, and an insulating pattern between the landing pad structures, the insulating pattern in contact with the bit line structures. Portions of the bit line structures extend in the second horizontal direction in the bit line trenches. Each of the landing pad structures includes a lower landing pad, arranged on a level lower than that of each of upper surfaces of the bit line structures, and an upper landing pad on the lower landing pad.

公开(公告)号：US20250031363A1

公开(公告)日：2025-01-23

申请号：US18413813

申请日：2024-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minju KANG ,  Jongmin KIM ,  Sangjae PARK ,  Sohyun PARK ,  Kiseok LEE

IPC: H10B12/00 ,  H10N50/80 ,  H10N70/00

Abstract: A semiconductor device includes a first active pattern including a first edge portion and a second edge portion spaced apart from the first edge portion in a first direction, a first word line between the first edge portion and the second edge portion and extending in a second direction intersecting the first direction, a bit line on the first edge portion and extending in a third direction intersecting the first direction and the second direction, and a storage node contact on the second edge portion, where the first edge portion includes a first top surface and a second top surface, and the second top surface of the first edge portion is closer to the second edge portion than the first top surface of the first edge portion.

公开(公告)号：US20240268130A1

公开(公告)日：2024-08-08

申请号：US18374718

申请日：2023-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungeun CHOI ,  Kiseok LEE

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device includes a lower bonding structure that includes a lower substrate, a lower dielectric structure on the lower substrate, and a transistor between the lower substrate and the lower dielectric structure, an upper bonding structure that includes an upper dielectric structure on the lower dielectric structure, an upper substrate on the upper dielectric structure, and a memory cell structure between the upper substrate and the upper dielectric structure, a connection structure on the upper bonding structure, and a first through via that electrically connects the transistor to the memory cell structure. The transistor overlaps the memory cell structure. The first through via penetrates the upper substrate and the upper dielectric structure.

公开(公告)号：US20240266308A1

公开(公告)日：2024-08-08

申请号：US18236501

申请日：2023-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Hyungeun CHOI ,  Keunnam KIM ,  Jinwoo HAN

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H10B12/00

CPC classification number: H01L24/06 ,  H01L23/5226 ,  H01L23/5283 ,  H10B12/315 ,  H10B12/482 ,  H01L2224/0603 ,  H01L2224/06102

Abstract: A semiconductor device includes a lower substrate, a lower dielectric structure on the lower substrate, a transistor between the lower substrate and the lower dielectric structure, a lower bonding pad in the lower dielectric structure, an upper dielectric structure on the lower dielectric structure, an upper substrate on the upper dielectric structure, a memory cell structure between the upper substrate and the upper dielectric structure, and an upper bonding pad in the upper dielectric structure. A top surface of the lower bonding pad is in contact with a bottom surface of the upper bonding pad. The lower bonding pad and the upper bonding pad overlap the memory cell structure.

公开(公告)号：US20240147706A1

公开(公告)日：2024-05-02

申请号：US18370149

申请日：2023-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keunui KIM ,  Kiseok LEE ,  Eunsuk JANG ,  Seokhan PARK ,  Seok-Ho SHIN ,  Joongchan SHIN ,  Moonyoung JEONG

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/315 ,  H10B12/482 ,  H10B12/50

Abstract: A semiconductor memory device may include a substrate, a bit line extending in a first direction on the substrate, a first word line and a second word line extending in a second direction to cross the bit line, a back-gate electrode extending in the second direction between the first word line and the second word line, first and second active patterns disposed between the first and second word lines and the back-gate electrode and connected to the bit line, contact patterns coupled to the first and second active patterns, respectively, a first back-gate capping pattern between the contact patterns and the back-gate electrode, and first gate capping patterns between the contact patterns and the first and second word lines. The first back-gate capping pattern and the first gate capping pattern may have first and second seams, which are extended in the second direction and are located at different vertical levels.

公开(公告)号：US20240147701A1

公开(公告)日：2024-05-02

申请号：US18238790

申请日：2023-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Eunju CHO ,  Keunnam KIM ,  Seokhan PARK ,  Seok-Ho SHIN ,  Joongchan SHIN ,  Heechan YOON

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/485 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor memory device may include a substrate including a cell array region and a connection region, bit lines provided on the substrate and extending in a first direction, first and second active patterns alternately arranged in the first direction on each of the bit lines, back-gate electrodes disposed between adjacent ones of the first and second active patterns and extended in a second direction to cross the bit lines, first and second word lines disposed adjacent to the first and second active patterns respectively and extending in the second direction, and a shielding conductive pattern including line portions, which are respectively disposed between adjacent ones of the bit lines, and a plate portion, which is connected in common to the line portions. A length of the line portions of the shielding conductive pattern in the first direction may be shorter than that of the bit lines.

公开(公告)号：US20230371235A1

公开(公告)日：2023-11-16

申请号：US18078217

申请日：2022-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyeok AHN ,  Kiseok LEE

IPC: H10B12/00

CPC classification number: H01L27/10814

Abstract: A semiconductor device includes a substrate including an active region, a word line structure crossing the active region and extending in a first direction, a bit line structure extending in a second direction, a bit line contact electrically connecting a first impurity region of the active region to the bit line structure, a storage node contact on a sidewall of the bit line structure and electrically connected to a second impurity region of the active region, and a contact barrier layer covering at least a portion of the bit line contact, wherein the bit line contact includes a lower portion having a first width and an upper portion on the lower portion and having a second width, the first width is greater than the second width, and the contact barrier layer covers a bottom surface and a side surface of the lower portion.