公开(公告)号：US11862220B2

公开(公告)日：2024-01-02

申请号：US17836228

申请日：2022-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjun Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Jongman Park ,  Dongsoo Woo ,  Kyunghwan Lee

IPC: G11C11/22 ,  G11C5/06

CPC classification number: G11C11/2273 ,  G11C5/06 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2275

Abstract: Provided is a memory device. The memory device may include a substrate, a ferroelectric field effect transistor disposed on the substrate, a first channel contacting a gate structure of the ferroelectric field effect transistor and extending in a vertical direction from the gate structure of the ferroelectric field effect transistor, a selection word line disposed at one side of the first channel, a first gate dielectric layer disposed between the first channel and the selection word line, and a cell word line disposed on top of the first channel.

公开(公告)号：US11621264B2

公开(公告)日：2023-04-04

申请号：US16999378

申请日：2020-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Satoru Yamada ,  Sungwon Yoo ,  Kyunghwan Lee ,  Jaeho Hong

IPC: H01L27/102 ,  H01L29/24 ,  H01L29/66 ,  H01L29/87 ,  H01L29/74 ,  H01L27/108 ,  H01L27/06

Abstract: A semiconductor memory device may include a first electrode and a second electrode, which are spaced apart from each other in a first direction, and a first semiconductor pattern, which is in contact with both of the first and second electrodes. The first semiconductor pattern may include first to fourth sub-semiconductor patterns, which are sequentially disposed in the first direction. The first and fourth sub-semiconductor patterns may be in contact with the first and second electrodes, respectively. The first and third sub-semiconductor patterns may be of a first conductivity type, and the second and fourth sub-semiconductor patterns may be of a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogen element.

公开(公告)号：US20220108741A1

公开(公告)日：2022-04-07

申请号：US17362138

申请日：2021-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAEHO HONG ,  Hyuncheol Kim ,  Yongseok Kim ,  Iigweon Kim ,  Hyeongwon Seo ,  Sungwon Yoo ,  Kyunghwan Lee

IPC: G11C11/402 ,  H01L27/102 ,  H01L29/66 ,  H01L29/749

Abstract: A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.

公开(公告)号：US20220028859A1

公开(公告)日：2022-01-27

申请号：US17191308

申请日：2021-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho HONG ,  Kyunghwan Lee ,  Hyuncheol Kim ,  Huijung Kim ,  Hyunmog Park ,  Kiseok Lee ,  Minhee Cho

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/24

Abstract: A memory device is provided. The memory device includes: a substrate; a memory unit provided on the substrate; a channel provided on the memory unit; a word line surrounded by the channel and extending in a first horizontal direction; a gate insulating layer interposed between the channel and the word line; and a bit line contacting an upper end of the channel and extending in a second horizontal direction that crosses the first horizontal direction.

公开(公告)号：US10651195B2

公开(公告)日：2020-05-12

申请号：US16168219

申请日：2018-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Byoung-Taek Kim ,  Tae Hun Kim ,  Dongkyun Seo ,  Junhee Lim

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/51 ,  H01L27/11556 ,  H01L27/11524

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.

公开(公告)号：US12268042B2

公开(公告)日：2025-04-01

申请号：US17746247

申请日：2022-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Dongsoo Woo ,  Kyunghwan Lee

IPC: H01L21/00 ,  H10K10/50 ,  H10K19/00 ,  H10K85/20

Abstract: A variable resistance memory device including a stack including insulating sheets and conductive sheets, which are alternatingly stacked on a substrate, the stack including a vertical hole vertically penetrating therethrough, a bit line on the stack, a conductive pattern electrically connected to the bit line and vertically extending in the vertical hole, and a resistance varying layer between the conductive pattern and an inner side surface of the stack defining the vertical hole may be provided. The resistance varying layer may include a first carbon nanotube electrically connected to the conductive sheets, and a second carbon nanotube electrically connected to the conductive pattern.

公开(公告)号：US12249651B2

公开(公告)日：2025-03-11

申请号：US17741219

申请日：2022-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Dongsoo Woo ,  Kyunghwan Lee

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/417

Abstract: A semiconductor device includes: a channel; a gate structure on the channel; a first source/drain arranged at a first end of the channel and including a metal; a first tunable band-gap layer arranged between the channel and the first source/drain and having a band gap that changes according to stress; a first electrostrictive layer between the gate structure and the first tunable band-gap layer, the first electrostrictive layer having a property of being deformed based on and upon application of an electric field; and a second source/drain at a second end of the channel.

公开(公告)号：US12230227B2

公开(公告)日：2025-02-18

申请号：US18370128

申请日：2023-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minkyung Lee ,  Youngdeog Koh ,  Kwangjoo Kim ,  Choongkeon Kim ,  Kyunghwan Lee

IPC: G09G3/34 ,  G02F1/167 ,  G02F1/1676

Abstract: A home appliance including a main body; and a door to open and close the main body; and an electrophoretic display (EPD) panel on the door and including a plate to cover a portion of the door and to allow light to pass through, a first electrode configured to allow light pass through and a second electrode between the plate and the door, and an electrophoretic layer between the first electrode and the second electrode, and including a color cell in which first charged particles having a first color, and second charged particles having a second color are accommodated, the first charged particles and the second charged particles being flowable within the color cell, the second charged particles have a different charge than the first charged particles.

公开(公告)号：US11996457B2

公开(公告)日：2024-05-28

申请号：US17443553

申请日：2021-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Ilgweon Kim ,  Seokhan Park ,  Kyunghwan Lee ,  Jaeho Hong

IPC: H01L29/423 ,  H01L23/482 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L23/4828 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first conductive pattern, a gate insulation pattern, a second conductive pattern and a second impurity region. Each of the semiconductor structures includes a first semiconductor pattern that has a linear shape that extends in a first direction and second semiconductor patterns that protrude from an upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion harrier pattern and a polysilicon pattern doped with impurities.

公开(公告)号：US20240119984A1

公开(公告)日：2024-04-11

申请号：US18544996

申请日：2023-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Hong ,  Hyuncheol Kim ,  Yongseok Kim ,  Ilgweon Kim ,  Hyeoungwon Seo ,  Sungwon Yoo ,  Kyunghwan Lee

IPC: G11C11/402 ,  G11C11/39 ,  H01L27/102 ,  H01L29/66 ,  H01L29/749

CPC classification number: G11C11/4023 ,  G11C11/39 ,  H01L27/1027 ,  H01L29/66363 ,  H01L29/749

Abstract: A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.