公开(公告)号：US12236099B2

公开(公告)日：2025-02-25

申请号：US18455668

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwan Woo ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Nayeon Kim ,  Jinin So

IPC: G06F12/00 ,  G06F3/06

Abstract: An accelerator module includes a plurality of memories and a controller. The controller includes a plurality of memory controllers, a plurality of processing units, and a managing circuit. The plurality of memory controllers and the plurality of memories form a plurality of memory sub-channels. The plurality of processing units perform computational operations on a plurality of data stored in or read from the plurality of memories. The managing circuit redistributes tasks performed by the plurality of processing units or changes connections between the plurality of memory controllers and the plurality of processing units in response to a first memory sub-channel and a first processing unit being in a heavy-workload state.

公开(公告)号：US20240281402A1

公开(公告)日：2024-08-22

申请号：US18460954

申请日：2023-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Jung ,  Younghyun Lee ,  Yongsuk Kwon ,  Kyungsoo Kim ,  Jinin So

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0002

Abstract: A computing system includes an interconnect device, a plurality of memory devices electrically coupled to communicate with the interconnect device, a plurality of host devices electrically coupled to communicate with the interconnect device and configured to generate requests for access to the plurality of memory devices via the interconnect device, and a plurality of congestion monitors. These congestion monitors are configured to generate congestion information by monitoring a congestion degree of signal transfers with respect to at least one of the plurality of memory devices and the interconnect device in real time. The computing system is also configured to control at least one of: a memory region allocation of the plurality of host devices to the plurality of memory devices, and a signal transfer path inside the interconnect device, based on the congestion information.

公开(公告)号：US20240248609A1

公开(公告)日：2024-07-25

申请号：US18455668

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwan Woo ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Nayeon Kim ,  Jinin So

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0683

Abstract: An accelerator module includes a plurality of memories and a controller. The controller includes a plurality of memory controllers, a plurality of processing units, and a managing circuit. The plurality of memory controllers and the plurality of memories form a plurality of memory sub-channels. The plurality of processing units perform computational operations on a plurality of data stored in or read from the plurality of memories. The managing circuit redistributes tasks performed by the plurality of processing units or changes connections between the plurality of memory controllers and the plurality of processing units in response to a first memory sub-channel and a first processing unit being in a heavy-workload state.

公开(公告)号：US20240201858A1

公开(公告)日：2024-06-20

申请号：US18322798

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nayeon Kim ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Jinin So ,  Kyoungwan Woo

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory includes: a request register configured to receive a first signal including a requester identifier using a first protocol from a host and configured to output a first priority corresponding to the requester identifier; a checker module configured to receive a second signal including a command and a request type from the host and using a second protocol that is different than the first protocol, where the checker module is configured to receive the first priority from the request register, and where the checker module is configured to determine a second priority of the command based on the first priority and the request type; a command generator configured to generate an internal command for memory operation based on the command; and a memory controller configured to schedule the internal command in a command queue based on the second priority.

公开(公告)号：US11531618B2

公开(公告)日：2022-12-20

申请号：US17157323

申请日：2021-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsoo Kim ,  Jinin So ,  Jong-Geon Lee ,  Yongsuk Kwon ,  Jin Jung ,  Jeonghyeon Cho

IPC: G06F12/0804 ,  G06F11/20 ,  G11C11/4093 ,  G11C11/4096 ,  H04N21/426

Abstract: A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.

公开(公告)号：US20210390049A1

公开(公告)日：2021-12-16

申请号：US17157323

申请日：2021-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsoo Kim ,  Jinin So ,  Jong-Geon Lee ,  Yongsuk Kwon ,  Jin Jung ,  Jeonghyeon Cho

IPC: G06F12/0804 ,  G06F11/20 ,  G11C11/4096 ,  G11C11/4093

Abstract: A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.

公开(公告)号：US12272423B2

公开(公告)日：2025-04-08

申请号：US17974940

申请日：2022-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sachin Suresh Upadhya ,  Eldho Pathiyakkara Thombra Mathew ,  Mayuresh Jyotindra Salelkar ,  Jinin So ,  Jonggeon Lee ,  Kyungsoo Kim

IPC: G11C7/10 ,  G11C7/22

Abstract: A method of operating a Near Memory Processing-Dual In-line Memory (NMP-DIMM) system, the method including: determining, by an adaptive latency module of the NMP-DIMM system, a synchronized read latency value for performing a read operation upon receiving a Multi-Purpose Register (MPR) read instruction from a host device communicatively connected with the NMP-DIMM system, wherein the MPR read instruction is received from the host device for training the NMP-DIMM system, wherein the synchronized read latency value is determined based on one or more read latency values associated with one or more memory units of the NMP-DIMM system; and synchronizing, by the adaptive latency module, one or more first type data paths and a second type data path in the NMP-DIMM system based on the determined synchronized read latency value.

公开(公告)号：US20240387552A1

公开(公告)日：2024-11-21

申请号：US18643149

申请日：2024-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyenhee Lee ,  Kyungsoo Kim

IPC: H01L27/118 ,  H03K19/20

Abstract: A semiconductor device includes: an active pattern extending on a substrate in a first direction; first to fourth channel structures stacked, in order, on one region of the active pattern; first to fourth gate structure respectively crossing the first to fourth channel structures, and extending in a second direction; first to fourth source/drain patterns, respectively, connected to both ends of the first to fourth channel structures; a plurality of upper contact vias electrically connecting each of a plurality of upper wiring lines to at least one of the first to fourth source/drain patterns; a plurality of lower wiring lines disposed on a lower surface of the substrate; and a plurality of lower contact vias penetrating through the substrate and electrically connecting each of the plurality of lower wiring lines to at least one of the first to fourth source/drain patterns.

公开(公告)号：US20230386534A1

公开(公告)日：2023-11-30

申请号：US17974940

申请日：2022-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sachin Suresh Upadhya ,  Eldho Pathiyakkara Thombra Mathew ,  Mayuresh Jyotindra Salelkar ,  Jinin So ,  Jonggeon Lee ,  Kyungsoo Kim

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1069 ,  G11C7/1066 ,  G11C7/227 ,  G11C7/1063

Abstract: A method of operating a Near Memory Processing-Dual In-line Memory (NMP-DIMM) system, the method including: determining, by an adaptive latency module of the NMP-DIMM system, a synchronized read latency value for performing a read operation upon receiving a Multi-Purpose Register (MPR) read instruction from a host device communicatively connected with the NMP-DIMM system, wherein the MPR read instruction is received from the host device for training the NMP-DIMM system, wherein the synchronized read latency value is determined based on one or more read latency values associated with one or more memory units of the NMP-DIMM system; and synchronizing, by the adaptive latency module, one or more first type data paths and a second type data path in the NMP-DIMM system based on the determined synchronized read latency value.

公开(公告)号：US20230028071A1

公开(公告)日：2023-01-26

申请号：US17715158

申请日：2022-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonggeon Lee ,  Jinin So ,  Yongsuk Kwon ,  Kyungsoo Kim ,  Ilkwon Yun ,  Jeonghyeon Cho

IPC: G06F13/40 ,  G06F13/16 ,  G06F9/30

Abstract: A memory module includes a device memory configured to store data and including a first memory area and a second memory area, and a controller including an accelerator circuit. The controller is configured to control the device memory, transmit a command to exclude the first memory area from the system memory map to a host processor in response to a mode change request, and modify a memory configuration register to exclude the first memory area from the memory configuration register. The accelerator circuit is configured to use the first memory area to perform an acceleration operation.