公开(公告)号：US11348629B2

公开(公告)日：2022-05-31

申请号：US17000009

申请日：2020-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Ryan Hatcher ,  Jorge A. Kittl

IPC: G11C11/16 ,  H01L43/06 ,  H01L43/04 ,  G06N3/063 ,  G06F7/50 ,  H01L43/10 ,  H01L43/08

Abstract: A non-volatile data retention circuit includes a complementary latch configured to generate and store complementary non-volatile spin states corresponding to an input signal when in a write mode, and to concurrently generate a first charge current signal and a second charge current corresponding to the complementary non-volatile spin states when in read mode, and a differential amplifier coupled to the complementary latch and configured to generate an output signal based on the first and second charge current signals.

公开(公告)号：US10790002B2

公开(公告)日：2020-09-29

申请号：US16290715

申请日：2019-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Ryan Hatcher ,  Jorge A. Kittl

IPC: G11C11/16 ,  G06N3/063 ,  G06F7/50 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  H01L43/08

Abstract: A non-volatile data retention circuit includes a complementary latch configured to generate and store complementary non-volatile spin states corresponding to an input signal when in a write mode, and to concurrently generate a first charge current signal and a second charge current corresponding to the complementary non-volatile spin states when in read mode, and a differential amplifier coupled to the complementary latch and configured to generate an output signal based on the first and second charge current signals.

公开(公告)号：US20220246190A1

公开(公告)日：2022-08-04

申请号：US17679601

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Ryan Hatcher ,  Jorge A. Kittl

IPC: G11C11/16 ,  G06N3/063 ,  G06F7/50 ,  H01L43/06 ,  H01L43/04 ,  H01L43/10 ,  H01L43/08

Abstract: A non-volatile data retention circuit includes a complementary latch configured to generate and store complementary non-volatile spin states corresponding to an input signal when in a write mode, and to concurrently generate a first charge current signal and a second charge current corresponding to the complementary non-volatile spin states when in read mode, and a differential amplifier coupled to the complementary latch and configured to generate an output signal based on the first and second charge current signals.

公开(公告)号：US11101320B2

公开(公告)日：2021-08-24

申请号：US16850691

申请日：2020-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan Hatcher ,  Titash Rakshit ,  Jorge Kittl ,  Rwik Sengupta ,  Dharmendar Palle ,  Joon Goo Hong

IPC: G11C11/15 ,  H01L27/22 ,  G11C11/16 ,  G11C13/00 ,  H01F10/32 ,  H01L43/02 ,  H01L27/24

Abstract: A weight cell, an electronic device and a device are provided. The weight cell includes a first resistive memory element and a second resistive memory element, a select transistor, and a layer of Spin Hall (SH) material disposed between the first resistive memory element and the second resistive memory element, the layer of the SH material including a first contact and a second contact. The first contact of the SH material is connected to a drain of the select transistor and the second contact of the SH material is connected to an external word line.

公开(公告)号：US20210133544A1

公开(公告)日：2021-05-06

申请号：US16849638

申请日：2020-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan Hatcher ,  Titash Rakshit ,  Jorge Kittl ,  Dharmendar Palle ,  JoonGoo Hong

IPC: G06N3/063

Abstract: A method and system are provided. The method includes mapping a binary matrix to an undirected graph form, applying a two-way graph partition algorithm to the mapped binary matrix that minimizes edge cuts between partitions in the mapped binary matrix, applying a greedy algorithm recursively to find a set of row or column permutations that maximizes a transfer of non-zeros from sparse blocks to nonsparse blocks, and sparsifying or densifying the binary matrix according to the applied greedy algorithm.

公开(公告)号：US20210118950A1

公开(公告)日：2021-04-22

申请号：US16850691

申请日：2020-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan Hatcher ,  Titash Rakshit ,  Jorge Kittl ,  Rwik Sengupta ,  Dharmendar Palle ,  Joon Goo Hong

IPC: H01L27/22 ,  H01L27/24 ,  G11C11/16 ,  H01L43/02 ,  G11C13/00 ,  H01F10/32

Abstract: A weight cell, an electronic device and a device are provided. The weight cell includes a first resistive memory element and a second resistive memory element, a select transistor, and a layer of Spin Hall (SH) material disposed between the first resistive memory element and the second resistive memory element, the layer of the SH material including a first contact and a second contact. The first contact of the SH material is connected to a drain of the select transistor and the second contact of the SH material is connected to an external word line.

公开(公告)号：US20210117769A1

公开(公告)日：2021-04-22

申请号：US17133427

申请日：2020-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Jorge A. Kittl ,  Ryan Hatcher

IPC: G06N3/063 ,  G06N3/04 ,  H01L27/112 ,  H01L27/11556 ,  G06N3/08

Abstract: A neuromorphic weight cell (NWC) including a resistor ladder including a plurality of resistors connected in series, and a plurality of shunting nonvolatile memory (NVM) elements, each of the shunting NVM elements being coupled in parallel to a corresponding one of the resistors.

公开(公告)号：US10909449B2

公开(公告)日：2021-02-02

申请号：US15678050

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Jorge A. Kittl ,  Ryan Hatcher

IPC: G06N3/063 ,  G06N3/04 ,  H01L27/112 ,  H01L27/11556 ,  G06N3/08 ,  G11C13/00

Abstract: A neuromorphic weight cell (NWC) including a resistor ladder including a plurality of resistors connected in series, and a plurality of shunting nonvolatile memory (NVM) elements, each of the shunting NVM elements being coupled in parallel to a corresponding one of the resistors.

公开(公告)号：US20190392881A1

公开(公告)日：2019-12-26

申请号：US16290715

申请日：2019-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Ryan Hatcher ,  Jorge A. Kittl

IPC: G11C11/16 ,  G06N3/063 ,  G06F7/50 ,  H01L43/08 ,  H01L43/06 ,  H01L43/04 ,  H01L43/10

Abstract: A non-volatile data retention circuit includes a complementary latch configured to generate and store complementary non-volatile spin states corresponding to an input signal when in a write mode, and to concurrently generate a first charge current signal and a second charge current corresponding to the complementary non-volatile spin states when in read mode, and a differential amplifier coupled to the complementary latch and configured to generate an output signal based on the first and second charge current signals.