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1.发明授权公开(公告)号：US11475933B2
公开(公告)日：2022-10-18
申请号：US16847741
申请日：2020-04-14
发明人： Ryan Hatcher , Titash Rakshit , Jorge Kittl , Joon Goo Hong , Dharmendar Palle
摘要： A method, system and electronic device for mitigating variance in a two transistor two resistive memory element (2T2R) circuit is provided. The method includes calculating a sum of a number of logical 1's in a column of bitcells in the 2T2R circuit, N, of an input vector, sensing output current values from each current line in the column of bitcells and calculating an inner product, M, of the input vector and the bitcells in the column in the 2T2R circuit based on the sensed output current values.
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2.发明授权公开(公告)号：US10832774B2
公开(公告)日：2020-11-10
申请号：US16448820
申请日：2019-06-21
发明人： Ryan M. Hatcher , Titash Rakshit , Jorge Kittl , Rwik Sengupta , Dharmendar Palle , Joon Goo Hong
摘要： A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, and a third FET, and a load resistor connected to a drain of the third FET.
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3.发明申请公开(公告)号：US20200279605A1
公开(公告)日：2020-09-03
申请号：US16448820
申请日：2019-06-21
发明人： Ryan M. Hatcher , Titash Rakshit , Jorge Kittl , Rwik Sengupta , Dharmendar Palle , Joon Goo Hong
摘要： A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, and a third FET, and a load resistor connected to a drain of the third FET.
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公开(公告)号：US20200265892A1
公开(公告)日：2020-08-20
申请号：US16448799
申请日：2019-06-21
发明人： Ryan M. HATCHER , Titash Rakshit , Jorge Kittl , Rwik Sengupta , Dharmendar Palle , Joon Goo Hong
摘要： A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, and a second FET and a second resistive memory element connected to a drain of the second FET. The drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET.
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公开(公告)号：US09614002B1
公开(公告)日：2017-04-04
申请号：US15238720
申请日：2016-08-16
CPC分类号： G11C11/16 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , H01L27/224 , H01L43/08 , H01L43/12
摘要： A bidirectional memory cell includes a write unit and a read unit. The write unit and the read unit each include an MTJ structure having a first and second pinned layers and a free layer. The first and second pinned layers are separated from the free layer by at least one tunnel barrier. The first pinned layer is electrically coupled to a first write line through a first diode. The second pinned layer is electrically connected to a second word line through a second diode. The free layer is electrically coupled to a first bit line. Additionally, the free layer of the read unit is magnetically coupled to the free layer of the write unit.
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公开(公告)号：US11101320B2
公开(公告)日：2021-08-24
申请号：US16850691
申请日：2020-04-16
发明人： Ryan Hatcher , Titash Rakshit , Jorge Kittl , Rwik Sengupta , Dharmendar Palle , Joon Goo Hong
摘要： A weight cell, an electronic device and a device are provided. The weight cell includes a first resistive memory element and a second resistive memory element, a select transistor, and a layer of Spin Hall (SH) material disposed between the first resistive memory element and the second resistive memory element, the layer of the SH material including a first contact and a second contact. The first contact of the SH material is connected to a drain of the select transistor and the second contact of the SH material is connected to an external word line.
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公开(公告)号：US20210133544A1
公开(公告)日：2021-05-06
申请号：US16849638
申请日：2020-04-15
发明人： Ryan Hatcher , Titash Rakshit , Jorge Kittl , Dharmendar Palle , JoonGoo Hong
IPC分类号： G06N3/063
摘要： A method and system are provided. The method includes mapping a binary matrix to an undirected graph form, applying a two-way graph partition algorithm to the mapped binary matrix that minimizes edge cuts between partitions in the mapped binary matrix, applying a greedy algorithm recursively to find a set of row or column permutations that maximizes a transfer of non-zeros from sparse blocks to nonsparse blocks, and sparsifying or densifying the binary matrix according to the applied greedy algorithm.
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8.发明申请公开(公告)号：US20210118950A1
公开(公告)日：2021-04-22
申请号：US16850691
申请日：2020-04-16
发明人： Ryan Hatcher , Titash Rakshit , Jorge Kittl , Rwik Sengupta , Dharmendar Palle , Joon Goo Hong
摘要： A weight cell, an electronic device and a device are provided. The weight cell includes a first resistive memory element and a second resistive memory element, a select transistor, and a layer of Spin Hall (SH) material disposed between the first resistive memory element and the second resistive memory element, the layer of the SH material including a first contact and a second contact. The first contact of the SH material is connected to a drain of the select transistor and the second contact of the SH material is connected to an external word line.
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公开(公告)号：US10510665B2
公开(公告)日：2019-12-17
申请号：US14931845
申请日：2015-11-03
发明人： Ganesh Hegde , Mark Rodder , Jorge Kittl , Chris Bowen
IPC分类号： H01L23/528 , H01L23/532 , H01L21/225 , H01L21/768
摘要： A diffusion barrier and a method to form the diffusion bather are disclosed. A trench structure is formed in an Inter Layer Dielectric (ILD). The ILD comprises a dielectric matrix having a first density. A dopant material layer is formed on the trench structure in which the dopant material layer comprises atoms of at least one of a rare-earth element. The ILD and the trench structure are annealed to form a dielectric matrix comprising a second density in one or more regions of the ILD on which the dopant material layer was formed that is greater than the first density. After annealing, the dielectric matrix comprising the second density includes increased bond lengths of oxygen-silicon bonds and/or oxygen-semiconductor bonds, increased bond angles of oxygen-silicon bonds and/or oxygen-semiconductor material bonds, and pores in the dielectric matrix are sealed compared to the dielectric matrix comprising the first density.
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公开(公告)号：US09653287B2
公开(公告)日：2017-05-16
申请号：US14919634
申请日：2015-10-21
发明人： Mark Rodder , Joon Hong , Jorge Kittl , Borna Obradovic
IPC分类号： H01L21/02 , H01L29/417 , H01L29/786 , H01L29/45 , H01L29/66 , H01L29/06 , H01L21/285
CPC分类号： H01L21/02603 , H01L21/28518 , H01L21/28531 , H01L29/0665 , H01L29/41733 , H01L29/41758 , H01L29/45 , H01L29/66742 , H01L29/78696
摘要： A field effect transistor (FET) and a method to form the FET are disclosed. The FET comprises a channel region comprising a nanosheet layer/sacrificial layer stack. The stack comprises at least one nanosheet layer/sacrificial layer pair. Each nanosheet layer/sacrificial layer pair comprises an end surface. A conductive material layer is formed on the end surface of the pairs, and a source/drain contact is formed on the conductive material layer. In one embodiment, the sacrificial layer of at least one pair further may comprise a low-k dielectric material proximate to the end surface of the pair. A surface of the low-k dielectric material proximate to the end surface of the pair is in substantial alignment with the end surface of the nanosheet layer. Alternatively, the surface of the low-k dielectric material proximate to the end surface of the pair is recessed with respect to the end surface of the nanosheet layer.
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