公开(公告)号：US20210124984A1

公开(公告)日：2021-04-29

申请号：US16839043

申请日：2020-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Malik Aqeel Anwar ,  Ryan Hatcher

IPC: G06K9/62 ,  G06N3/04 ,  G06N3/08 ,  G06F17/16 ,  G06K9/46

Abstract: A method of pipelining inference of a neural network, which includes an i-th layer (i being an integer greater than zero) and an (i+1)-th layer, includes processing, for a first input image, first i-th values of the i-th layer to generate first (i+1)-th values for the (i+1)-th layer, processing, for the first input image, the first (i+1)-th values of the (i+1)-th layer to generate output values, and concurrently with processing, for the first image, the (i+1)-th values, processing, for a second input image, second i-th values of the i-th layer to generate second (i+1)-th values.

公开(公告)号：US11475933B2

公开(公告)日：2022-10-18

申请号：US16847741

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan Hatcher ,  Titash Rakshit ,  Jorge Kittl ,  Joon Goo Hong ,  Dharmendar Palle

IPC: G11C11/16 ,  G06F17/16 ,  G06F17/17 ,  G06G7/16

Abstract: A method, system and electronic device for mitigating variance in a two transistor two resistive memory element (2T2R) circuit is provided. The method includes calculating a sum of a number of logical 1's in a column of bitcells in the 2T2R circuit, N, of an input vector, sensing output current values from each current line in the column of bitcells and calculating an inner product, M, of the input vector and the bitcells in the column in the 2T2R circuit based on the sensed output current values.

公开(公告)号：US20210124588A1

公开(公告)日：2021-04-29

申请号：US16838971

申请日：2020-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Malik Aqeel Anwar ,  Ryan Hatcher

IPC: G06F9/38 ,  G06N3/02 ,  G06F17/16 ,  G06T1/20

Abstract: A method of pipelining inference of a neural network, which includes an i-th layer (i being an integer greater than zero), an (i+1)-th layer, and an (i+2)-th layer, includes processing a first set of i-th values of the i-th layer to generate (i+1)-th values for the (i+1)-th layer, determining a quantity of the (i+1)-th values as being sufficient for processing, and in response to the determining, processing the (i+1)-th values to generate an output value for the (i+2)-th layer while concurrently processing a second set of i-th values of the i-th layer.

公开(公告)号：US20180300618A1

公开(公告)日：2018-10-18

申请号：US15678050

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Jorge A. Kittl ,  Ryan Hatcher

IPC: G06N3/063 ,  H01L27/112 ,  G06N3/04

Abstract: A neuromorphic weight cell (NWC) including a resistor ladder including a plurality of resistors connected in series, and a plurality of shunting nonvolatile memory (NVM) elements, each of the shunting NVM elements being coupled in parallel to a corresponding one of the resistors.

公开(公告)号：US10026751B2

公开(公告)日：2018-07-17

申请号：US15210867

申请日：2016-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Rwik Sengupta ,  Wei-E Wang ,  Ryan Hatcher ,  Mark S. Rodder

IPC: H01L27/01 ,  H01L27/12 ,  H01L23/522 ,  H01L23/528 ,  H01L29/24 ,  H01L29/45 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/84 ,  H01L29/10

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include one or more transition metal dichalcogenide materials such as MoS2, WS2, WSe2, and/or combinations thereof.

公开(公告)号：US11769043B2

公开(公告)日：2023-09-26

申请号：US16839043

申请日：2020-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Malik Aqeel Anwar ,  Ryan Hatcher

IPC: G06T1/20 ,  G06N3/063 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08 ,  G06F18/21

CPC classification number: G06N3/063 ,  G06F17/16 ,  G06F18/21 ,  G06N3/04 ,  G06N3/08

Abstract: A method of pipelining inference of a neural network, which includes an i-th layer (i being an integer greater than zero) and an (i+1)-th layer, includes processing, for a first input image, first i-th values of the i-th layer to generate first (i+1)-th values for the (i+1)-th layer, processing, for the first input image, the first (i+1)-th values of the (i+1)-th layer to generate output values, and concurrently with processing, for the first image, the (i+1)-th values, processing, for a second input image, second i-th values of the i-th layer to generate second (i+1)-th values.

公开(公告)号：US11556768B2

公开(公告)日：2023-01-17

申请号：US16849638

申请日：2020-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan Hatcher ,  Titash Rakshit ,  Jorge Kittl ,  Dharmendar Palle ,  Joon Goo Hong

IPC: G06N3/063 ,  G06N3/02

Abstract: A method and system are provided. The method includes mapping a binary matrix to an undirected graph form, applying a two-way graph partition algorithm to the mapped binary matrix that minimizes edge cuts between partitions in the mapped binary matrix, applying a greedy algorithm recursively to find a set of row or column permutations that maximizes a transfer of non-zeros from sparse blocks to nonsparse blocks, and sparsifying or densifying the binary matrix according to the applied greedy algorithm.

公开(公告)号：US20170098661A1

公开(公告)日：2017-04-06

申请号：US15210867

申请日：2016-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Rwik Sengupta ,  Wei-E Wang ,  Ryan Hatcher ,  Mark S. Rodder

IPC: H01L27/12 ,  H01L23/528 ,  H01L29/24 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/84 ,  H01L23/522 ,  H01L29/45

CPC classification number: H01L27/12 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/528 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/78681

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include one or more transition metal dichalcogenide materials such as MoS2, WS2, WSe2, and/or combinations thereof.

公开(公告)号：US12260324B2

公开(公告)日：2025-03-25

申请号：US17133427

申请日：2020-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Jorge A. Kittl ,  Ryan Hatcher

IPC: G06N3/04 ,  G06N3/0442 ,  G06N3/063 ,  G06N3/065 ,  G11C11/54 ,  G11C11/56 ,  H10B20/00 ,  H10B41/27 ,  G06N3/045 ,  G11C13/00 ,  H01L21/762

Abstract: A neuromorphic weight cell (NWC) including a resistor ladder including a plurality of resistors connected in series, and a plurality of shunting nonvolatile memory (NVM) elements, each of the shunting NVM elements being coupled in parallel to a corresponding one of the resistors.

公开(公告)号：US11769540B2

公开(公告)日：2023-09-26

申请号：US17679601

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Ryan Hatcher ,  Jorge A. Kittl

IPC: G11C11/16 ,  G06N3/063 ,  G06F7/50 ,  H10N50/10 ,  H10N50/85 ,  H10N52/00 ,  H10N52/80

CPC classification number: G11C11/1675 ,  G06F7/50 ,  G06N3/063 ,  G11C11/1673 ,  H10N50/10 ,  H10N50/85 ,  H10N52/00 ,  H10N52/80 ,  G06F2207/4824

Abstract: A non-volatile data retention circuit includes a complementary latch configured to generate and store complementary non-volatile spin states corresponding to an input signal when in a write mode, and to concurrently generate a first charge current signal and a second charge current corresponding to the complementary non-volatile spin states when in read mode, and a differential amplifier coupled to the complementary latch and configured to generate an output signal based on the first and second charge current signals.