公开(公告)号：US20210398890A1

公开(公告)日：2021-12-23

申请号：US17177305

申请日：2021-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGKYU KIM ,  SEOKHYUN LEE ,  KYOUNG LIM SUK ,  JAEGWON JANG ,  GWANGJAE JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package may include a redistribution substrate, a connection terminal, and a semiconductor chip sequentially stacked. The redistribution substrate may include an insulating layer, a plurality of redistribution patterns, which are vertically stacked in the insulating layer, and each of which includes interconnection and via portions, and a bonding pad on the interconnection portion of the topmost redistribution pattern. The topmost redistribution pattern and the bonding pad may include different metallic materials. The bonding pad may have first and second surfaces opposite to each other. The first surface of the bonding pad may be in contact with a top surface of the interconnection portion of the topmost redistribution pattern. A portion of the second surface of the bonding pad may be in contact with the connection terminal. The insulating layer may be extended to be in contact with the remaining portion of the second surface.

公开(公告)号：US20210193636A1

公开(公告)日：2021-06-24

申请号：US17179470

申请日：2021-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYOUNG LIM SUK ,  SEOKHYUN LEE

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/522 ,  H01L23/528

Abstract: A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.

公开(公告)号：US20190051607A1

公开(公告)日：2019-02-14

申请号：US16010872

申请日：2018-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung Lim SUK ,  SEOKHYUN LEE

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/14 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: Insulating layers of a redistribution layer of a semiconductor package may be formed as a polymer film having inorganic fillers formed therein. The inorganic fillers may trap reactive materials to inhibit and/or substantially prevent the metal conductors, such as chip pads of the semiconductor chip being packaged, from being damaged by the reactive material. As a result, the reliability and the durability of the semiconductor package may be improved.

公开(公告)号：US20230245966A1

公开(公告)日：2023-08-03

申请号：US18130760

申请日：2023-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYOUNG LIM SUK ,  SEOKHYUN LEE

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/49816 ,  H01L25/105 ,  H01L24/08 ,  H01L24/16 ,  H01L24/96 ,  H01L24/97 ,  H01L21/4857 ,  H01L21/486 ,  H01L2224/08235 ,  H01L2224/16227 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/182 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.

公开(公告)号：US20230101149A1

公开(公告)日：2023-03-30

申请号：US17843967

申请日：2022-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： TAEWON YOO ,  JONGYOUN KIM ,  KYOUNG LIM SUK ,  SEOKHYUN LEE ,  HYEONJEONG HWANG

IPC: H01L23/367 ,  H01L25/10 ,  H01L23/31 ,  H01L25/18

Abstract: A semiconductor package is disclosed. The semiconductor package may include a first redistribution substrate including a first insulating layer and a first redistribution pattern, a lower semiconductor chip mounted on the first redistribution substrate, a conductive structure disposed on the first redistribution substrate and horizontally spaced apart from the lower semiconductor chip, a first mold layer interposed between the first redistribution substrate and the second redistribution substrate to cover the lower semiconductor chip and the conductive structure, a second redistribution substrate on the first redistribution substrate, the second redistribution substrate including a second insulating layer and a second redistribution pattern, a first heat-dissipation pattern interposed between the lower semiconductor chip and the second insulating layer, and a heat-dissipation pad on the conductive structure. A top surface of the first heat-dissipation pattern may be located at a level higher than a top surface of the conductive structure.

公开(公告)号：US20230058497A1

公开(公告)日：2023-02-23

申请号：US17852542

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYOUNG LIM SUK ,  BANGWEON LEE ,  SEOKHYUN LEE

IPC: H01L23/48 ,  H01L25/10 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate, a first molding layer on the package substrate and surrounding the first semiconductor chip, a redistribution layer on the first molding layer, a first through via that vertically penetrates the first molding layer and connects the package substrate to the redistribution layer, a second semiconductor chip mounted on the redistribution layer, a second molding layer on the redistribution layer and surrounding the second semiconductor chip, and a second through via that vertically penetrates the second molding layer and is connected to the redistribution layer. A first width of the first through via is less than a second width of the second through via. The second through via is electrically floated from a signal circuit of the second semiconductor chip.

公开(公告)号：US20220310577A1

公开(公告)日：2022-09-29

申请号：US17501108

申请日：2021-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： DOOHWAN LEE ,  SEOKHYUN LEE ,  JEONGHO LEE

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package may include a first redistribution layer, a passive device disposed on a top surface of the first redistribution layer, a bridge structure disposed on the top surface of the first redistribution layer and laterally spaced apart from the passive device, a second redistribution layer disposed on and electrically connected to the passive device and the bridge structure, conductive structures disposed between the first redistribution layer and the second redistribution layer and laterally spaced apart from the passive device and the bridge structure, a first semiconductor chip mounted on a top surface of the second redistribution layer, and a second semiconductor chip mounted on the top surface of the second redistribution layer. The conductive structures may include a signal structure and a ground/power structure, which is laterally spaced apart from the signal structure and has a width larger than the signal structure.

公开(公告)号：US20220102282A1

公开(公告)日：2022-03-31

申请号：US17317368

申请日：2021-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYOUNG LIM SUK ,  SEOKHYUN LEE ,  JAEGWON JANG

IPC: H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate that has a first trench that extends through a top surface of the redistribution substrate, a first semiconductor chip on the redistribution substrate, a capacitor chip on a bottom surface of the first semiconductor chip, and an under-fill layer on the bottom surface of the first semiconductor chip. The redistribution substrate includes a plurality of dielectric layers vertically stacked, a plurality of redistribution patterns in each of the dielectric layers, and a plurality of dummy redistribution patterns in the first trench. The dummy redistribution patterns vertically overlap the first semiconductor chip. An uppermost surface of the dummy redistribution pattern is located at a level higher than a level of a bottom surface of the first trench.

公开(公告)号：US20210118788A1

公开(公告)日：2021-04-22

申请号：US16885546

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEOKHYUN LEE ,  GWANGJAE JEON

IPC: H01L23/498

Abstract: Disclosed are redistribution substrates and semiconductor packages including the same. For example, a redistribution substrate including a dielectric pattern, and a first redistribution pattern in the dielectric pattern is provided. The first redistribution pattern may include: a first via part having a first via seed pattern and a first via conductive pattern on the first via seed pattern, and a first wiring part having a first wiring seed pattern and a first wiring conductive pattern, the first wiring part being disposed on the first via part and having a horizontal width that is different from a horizontal width of the first via part. Additionally, the first wiring seed pattern may cover a bottom surface and a sidewall surface of the first wiring conductive pattern, and the first via conductive pattern is directly connected to the first wiring conductive pattern.

公开(公告)号：US20210074754A1

公开(公告)日：2021-03-11

申请号：US17101642

申请日：2020-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAEGWON JANG ,  SEOKHYUN LEE ,  KYOUNG LIM SUK

IPC: H01L27/146

Abstract: A semiconductor package includes a first redistribution layer, a first semiconductor chip on the first redistribution layer, a molding layer covering the first semiconductor chip, metal pillars around the first semiconductor chip and connected to the first redistribution layer, a second redistribution layer on the molding layer and connected to the metal pillars, and a second semiconductor chip on the second redistribution layer. The metal pillars extend through the molding layer. When viewed in plan, the second semiconductor chip overlaps the first semiconductor chip and the metal pillars. A method of manufacturing the semiconductor package obtains a wafer map from a first substrate that includes a plurality of first semiconductor chips and uses the wafer map in selectively stacking second semiconductor chips on the first semiconductor chips.