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    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    11.
    发明公开
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20230290783A1

    公开(公告)日：2023-09-14

    申请号：US18059639

    申请日：2022-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jeongsoon Kong ,  Myung Gil Kang ,  Sanghoon Baek

    IPC: H01L27/118

    CPC classification number: H01L27/11807 ,  H01L2027/11831 ,  H01L2027/11853 ,  H01L2027/11881

    Abstract: A semiconductor device includes a substrate including an N-stack cell, a buffer cell and an M-stack cell that are on the substrate, the buffer cell being between the N-stack and M-stack cells, an active pattern extending from the N-stack cell to the M-stack cell via the buffer cell, an N-stack channel pattern on the active pattern of the N-stack cell, an M-stack channel pattern on the active pattern of the M-stack cell, a dummy channel pattern on the active pattern of the buffer cell, an N-stack epitaxial pattern between the N-stack channel pattern and the dummy channel pattern, and an M-stack epitaxial pattern between the M-stack channel pattern and the dummy channel pattern. The N-stack channel pattern includes stacked N semiconductor patterns. The M-stack channel pattern includes stacked M semiconductor patterns. Each of N and M is an integer number of 2 or more, and M is greater than N.

    SEMICONDUCTOR DEVICES HAVING IMPROVED LAYOUT DESIGNS, AND METHODS OF DESIGNING AND FABRICATING THE SAME
    12.
    发明申请
    SEMICONDUCTOR DEVICES HAVING IMPROVED LAYOUT DESIGNS, AND METHODS OF DESIGNING AND FABRICATING THE SAME 有权

    公开(公告)号：US20220189944A1

    公开(公告)日：2022-06-16

    申请号：US17373510

    申请日：2021-07-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Ho Do ,  Sanghoon Baek

    IPC: H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  G06F30/392

    Abstract: A semiconductor device includes a first logic gate defined within a first unit cell footprint on a semiconductor substrate. The first logic gate includes a first field effect transistor including a first gate electrode and a first source/drain region, and a second field effect transistor including a second gate electrode and a second source/drain region. A first wiring pattern is provided, which extends in a first direction across a portion of the first unit cell footprint. The first wiring pattern is electrically connected to at least one of the first gate electrode and the second source/drain region, and has: (i) a first terminal end within a perimeter of the first unit cell footprint, and (ii) a second terminal end, which extends outside the perimeter of the first unit cell footprint but is not electrically connected to any current carrying region of any semiconductor device that is located outside the perimeter of the first unit cell footprint.

    Semiconductor device and method of fabricating the same
    14.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US09640444B2

    公开(公告)日：2017-05-02

    申请号：US14807220

    申请日：2015-07-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung-Ho Do ,  Sanghoon Baek ,  Sang-Kyu Oh ,  Kwanyoung Chun ,  Sunyoung Park ,  Taejoong Song

    IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/02

    CPC classification number: H01L21/823871 ,  H01L27/0207 ,  H01L27/092

    Abstract: Provided is a method of fabricating a semiconductor device with a field effect transistor. The method may include forming a first gate electrode and a second gate electrode extending substantially parallel to each other and each crossing a PMOSFET region on a substrate and an NMOSFET region on the substrate; forming an interlayered insulating layer covering the first gate electrode and the second gate electrode; patterning the interlayered insulating layer to form a first sub contact hole on the first gate electrode, the first sub contact hole being positioned between the PMOSFET region and the NMOSFET region, when viewed in a plan view; and patterning the interlayered insulating layer to form a first gate contact hole and to expose a top surface of the second gate electrode, wherein the first sub contact hole and the first gate contact hole form a single communication hole.

    Semiconductor devices and methods of forming the same
    15.
    发明授权
    Semiconductor devices and methods of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US09449970B2

    公开(公告)日：2016-09-20

    申请号：US14829650

    申请日：2015-08-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Ho Do ,  Sanghoon Baek ,  Sunyoung Park ,  Moo-Gyu Bae ,  Taejoong Song

    IPC: H01L29/76 ,  H01L29/94 ,  H01L27/088 ,  H01L27/02 ,  H01L29/06 ,  H01L27/118

    CPC classification number: H01L27/088 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/0642 ,  H01L2027/11874

    Abstract: A semiconductor device includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a third gate structure extending in the first direction and provided between the first and second gate structures, a first contact connected to the first gate structure and having a first width in the second direction, a second contact connected to the second gate structure and having a second width in the second direction, and a third contact connected to the third gate structure and having a third width in the second direction. The first, second, and third contacts may be aligned with each other in the second direction to constitute one row. The first and second widths may be greater than the third width.

    Abstract translation: 半导体器件包括在第一方向上延伸并且沿与第一方向相交的第二方向彼此间隔开的第一和第二栅极结构，在第一方向上延伸并设置在第一和第二栅极结构之间的第三栅极结构， 连接到第一栅极结构并且具有在第二方向上的第一宽度的第二接触，连接到第二栅极结构并且在第二方向上具有第二宽度的第二接触，以及连接到第三栅极结构并具有第三栅极结构的第三接触 宽度在第二个方向。 第一，第二和第三触点可以在第二方向上彼此对准以构成一行。 第一和第二宽度可以大于第三宽度。

    Semiconductor devices
    16.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US12159834B2

    公开(公告)日：2024-12-03

    申请号：US17532052

    申请日：2021-11-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungho Do ,  Sanghoon Baek

    IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

    Abstract: Disclosed is a semiconductor device comprising a mixed height cell on a substrate, and a first power line and a second power line that run across the mixed height cell. First to third line tracks are defined between the first power line and the second power line. A fourth line track is defined adjacent to the second power line. The second power line is between the third line track and the fourth line track. The mixed height cell includes a plurality of lower lines aligned with the first to fourth line tracks. A cell height of the mixed height cell is about 1.25 times to about 1.5 times a distance between a first point of the first power line and a corresponding second point of the second power line.

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