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公开(公告)号：US11709629B2
公开(公告)日：2023-07-25
申请号：US17455037
申请日：2021-11-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yonghyuk Choi , Jaeduk Yu , Sangwan Nam , Sangwon Park , Daeseok Byeon , Bongsoon Lim
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679 , G11C16/0483 , G11C16/08 , G11C16/24 , H10B41/27 , H10B43/27
Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.
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公开(公告)号：US11205471B2
公开(公告)日：2021-12-21
申请号：US16935712
申请日：2020-07-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yonghyuk Choi , Sangwan Nam
IPC: G11C16/04 , G11C11/408 , G11C5/02 , G11C11/409 , G11C5/06 , G11C11/4074
Abstract: A memory device includes a memory cell array including cell strings, respectively connected between string select lines and ground select lines, and wordlines connected to memory cells, a control logic to generate a first voltage provided to the string select lines, and a second voltage provided to the ground select lines, and to adjust voltage levels of the first and second voltages to control a channel boosting level of the cell strings, and a row decoder to provide a read voltage, a read pass voltage, and the first and second voltages to the memory cell array under control of the control logic. The control logic generates one of the first and second voltage as a pre-pulse voltage. The row decoder provides a third voltage to at least one of the wordlines.
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公开(公告)号：US20210149598A1
公开(公告)日：2021-05-20
申请号：US16918310
申请日：2020-07-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yonghyuk Choi , Jaeduk Yu , Sangwan Nam , Sangwon Park , Daeseok Byeon , Bongsoon Lim
Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.
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公开(公告)号：US20250031376A1
公开(公告)日：2025-01-23
申请号：US18582722
申请日：2024-02-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junil Lee , Yongjun Kim , Chanho Kim , Sangwan Nam , Ryoongbin Lee
Abstract: A semiconductor device may include a first semiconductor structure including a substrate, an active region in the substrate, a device isolation region defining the active region, and a capacitor structure on the device isolation region and vertically overlapping the device isolation region. The capacitor structure may include a first electrode structure extending in a first direction and including first capacitor electrodes stacked in the first direction, a second electrode structure including second capacitor electrodes stacked in the first direction, and a first insulating structure between the first electrode structure and the second electrode structure. Each of the first capacitor electrodes and the second capacitor electrodes are alternately arranged and spaced apart from each other in a second direction parallel to an upper surface of the substrate, extend in a third direction perpendicular to the first direction and the second direction, and has a plate shape.
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公开(公告)号：US12190954B2
公开(公告)日：2025-01-07
申请号：US17817408
申请日：2022-08-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hanjun Lee , Byungsoo Kim , Sangwan Nam
Abstract: A program method includes applying a first voltage to a plurality of bit lines, applying a second voltage to a common source line (CSL), and performing a program loop by applying a program voltage and a verify voltage to each of a plurality of ground selection lines (GSLs) positioned between one bit line among the plurality of bit lines and the CSL. The program loop is performed on both a program completed cell in which a program is completed by applying the program voltage and a program target cell.
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Patent Agency Ranking
公开(公告)号：US12181953B2
公开(公告)日：2024-12-31
申请号：US18374717
申请日：2023-09-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wandong Kim , Jinyoung Kim , Sehwan Park , Hyun Seo , Sangwan Nam
Abstract: An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data; calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.
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17.发明公开公开(公告)号：US20240233804A1
公开(公告)日：2024-07-11
申请号：US18404411
申请日：2024-01-04
Applicant: Samsung Electronics Co., LTD.
Inventor： Jayang YOON , Chihyun Kim , Sangwan Nam , Chiweon Yoon , Hyeongdo Choi
IPC: G11C11/4074 , G11C11/4076 , G11C11/4099
CPC classification number: G11C11/4074 , G11C11/4076 , G11C11/4099
Abstract: Disclosed is a memory device in which at least one word line or bit line is charged by a plurality of charging terminals. The memory device includes a first charging terminal for supplying a first voltage to the at least one word line or bit line, and a second charging terminal for suppling a second voltage to the at least one word line or bit line when voltage supply by the first charging terminal is completed. The supply of the second voltage starts when a charged voltage of the at least one word line or bit line, charged by using the first voltage, satisfies a first reference condition.
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公开(公告)号：US11942154B2
公开(公告)日：2024-03-26
申请号：US17825764
申请日：2022-05-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hongsoo Jeon , Bongsoon Lim , Sangwan Nam
CPC classification number: G11C16/0433 , G11C5/063 , G11C16/08 , G11C16/20
Abstract: A nonvolatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes word-lines, at least one string selection line, at least one ground selection line, and a memory cell array including at least one memory block. The second semiconductor includes a first address decoder and a second address decoder. The first address decoder is disposed under a first extension region adjacent to a first side of a cell region and includes a plurality of first pass transistors driving the word-lines, the at least one string selection line, and the at least one ground selection line. The second address decoder is disposed under a second extension region adjacent to a second side of the cell region and includes a plurality of second pass transistors driving the at least one string selection line and the at least one ground selection line.
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19.发明申请公开(公告)号：US20230013747A1
公开(公告)日：2023-01-19
申请号：US17935502
申请日：2022-09-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghyuk Choi , Sangwan Nam , Jaeduk Yu , Sangwon Park , Bongsoon Lim
Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.
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公开(公告)号：US11501847B2
公开(公告)日：2022-11-15
申请号：US17022967
申请日：2020-09-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghyuk Choi , Sangwan Nam , Jaeduk Yu , Sangwon Park , Bongsoon Lim
Abstract: A nonvolatile memory device includes memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, is connected to the memory cell region by the first metal pad and the second metal pad and includes including an address decoder and a page buffer circuit located on a first substrate. A memory cell array is provided in the memory cell region, which includes a first vertical structure on a second substrate. The first vertical structure includes first sub-blocks and first via areas in which one or more through-hole vias are provided, and through-hole vias pass through the first vertical structure. A control circuit in the peripheral circuit region groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.
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