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    NON-VOLATILE MEMORY DEVICE FOR DETECTING DEFECTS OF BIT LINES AND WORD LINES
    3.
    发明公开
    NON-VOLATILE MEMORY DEVICE FOR DETECTING DEFECTS OF BIT LINES AND WORD LINES 审中-公开

    公开(公告)号：US20230144141A1

    公开(公告)日：2023-05-11

    申请号：US17972300

    申请日：2022-10-24

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Junyoung Ko ,  Sangwan Nam ,  Youse Kim ,  Heewon Kim

    IPC分类号： G11C7/10 ,  G06F11/10

    CPC分类号： G11C7/1057 ,  G06F11/1076

    摘要： Provided is a non-volatile memory device. The non-volatile memory device includes: a memory cell array including cell strings, each including memory cells respectively connected to word lines; a page buffer circuit including page buffers respectively connected to the memory cells through bit lines, wherein a first page buffer is connected to a first cell string through a first bit line; a control logic circuit configured to control a pre-sensing operation to disconnect the first bit line and the first cell string from each other during a pre-sensing period for detecting a defect of the first bit line and control a post-sensing operation to connect the first bit line and the first cell string to each other in a post-sensing period for detecting defects of the word lines and the first bit line; and a defect detection circuit configured to detect defects of the word lines based the sensing operations.

    Nonvolatile memory device
    5.
    发明授权
    Nonvolatile memory device 有权

    公开(公告)号：US11200002B2

    公开(公告)日：2021-12-14

    申请号：US16918310

    申请日：2020-07-01

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Yonghyuk Choi ,  Jaeduk Yu ,  Sangwan Nam ,  Sangwon Park ,  Daeseok Byeon ,  Bongsoon Lim

    IPC分类号： G06F3/00 ,  G06F3/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11582

    摘要： A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

    Nonvolatile memory device and method of detecting wordline defect of the same
    8.
    发明授权
    Nonvolatile memory device and method of detecting wordline defect of the same 有权

    公开(公告)号：US11915773B2

    公开(公告)日：2024-02-27

    申请号：US17693571

    申请日：2022-03-14

    申请人： Samsung Electronics Co., Ltd.

    发明人： Kyunghae Lee ,  Buil Nam ,  Jinsun Yeom ,  Sangwan Nam ,  Jaein Lee

    IPC分类号： G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C29/12 ,  G11C29/38

    CPC分类号： G11C29/38 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  G11C29/12005

    摘要： A nonvolatile memory device includes a memory cell array, a voltage generator, a voltage path circuit and a wordline defect detection circuit. The memory cell array includes memory cells and wordlines connected to the memory cells. The voltage generator generates a wordline voltage applied to the wordlines. The voltage path circuit between the voltage generator and the memory cell array transfers the wordline voltage to the wordlines. The wordline defect detection circuit is connected to a measurement node between the voltage generator and the voltage path circuit. The wordline defect detection circuit measures a path leakage current of the voltage path circuit based on a measurement voltage of the measurement node to generate an offset value corresponding to the path leakage current in a compensation mode and determines defect of each wordline of the wordlines based on the offset value and the measurement voltage in a defect detection mode.

    Page buffer including latches and memory device including the page buffer
    9.
    发明授权
    Page buffer including latches and memory device including the page buffer 有权

    公开(公告)号：US11848069B2

    公开(公告)日：2023-12-19

    申请号：US17718070

    申请日：2022-04-11

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Keeho Jung ,  Sangwan Nam ,  Hyunggon Kim

    IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C7/06 ,  G11C7/12

    CPC分类号： G11C7/1039 ,  G11C7/065 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/12

    摘要： The memory device includes a page buffer circuit including a page buffer connected to each of a plurality of bit lines. The page buffer includes at least one additional latch and N number of data latches, and a control logic circuit that controls a setting of the page buffer. Based on a first setting, data programmed in a current program operation is stored in some of the N data latches and the at least one additional latch, and data which is to be programmed in a next program operation before the current program operation is completed is stored in some other of the N data latches and the at least one additional latches. Based on a second setting, externally provided data is not stored in the at least one additional latch in the current program operation and the next program operation.