公开(公告)号：US11749326B2

公开(公告)日：2023-09-05

申请号：US17862718

申请日：2022-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun Shin ,  Tae-Young Oh

IPC: G11C8/06 ,  G11C8/18 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G06F3/06 ,  G06F13/16

CPC classification number: G11C8/06 ,  G06F3/06 ,  G06F13/1689 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076 ,  G11C7/1057

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US11715507B2

公开(公告)日：2023-08-01

申请号：US17387036

申请日：2021-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun Shin ,  Tae-Young Oh

IPC: G11C8/06 ,  G11C8/18 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G06F3/06 ,  G06F13/16

CPC classification number: G11C8/06 ,  G06F3/06 ,  G06F13/1689 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076 ,  G11C7/1057

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US11327838B2

公开(公告)日：2022-05-10

申请号：US16389080

申请日：2019-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hwan Park ,  Tae-Young Oh ,  Hyung-Joon Chi ,  Kyung-Soo Ha ,  Hyong-Ryol Hwang

IPC: G06F11/10 ,  G11C7/22

Abstract: A memory device includes: a first memory bank and a second memory bank; a control logic configured to receive a command and control an internal operation of the memory device; and an error correction code (ECC) circuit configured to retain in a latch circuit first read data read from the first memory bank in response to a first masked write (MWR) command for the first memory bank based on a latch control signal from the control logic, generate a first parity from data in which the first read data retained in the latch circuit is merged with first write data corresponding to the first MWR command in response to a first write control signal received from the control logic, and control an ECC operation to retain in the latch circuit second read data read from the second memory bank based on the latch control signal.

公开(公告)号：US11282555B2

公开(公告)日：2022-03-22

申请号：US17190656

申请日：2021-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Ran Kim ,  Seong-Hwan Jeon ,  Tae-Young Oh

IPC: G06F1/12 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/10 ,  G06F13/16

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.

公开(公告)号：US10535394B2

公开(公告)日：2020-01-14

申请号：US16039404

申请日：2018-07-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hwa Kim ,  Tae-Young Oh ,  Jin-Hun Jang ,  Kyung-Soo Ha

IPC: G11C11/4074

Abstract: A memory device includes a first switch for switching a first power voltage and transmitting the first power voltage to a common node of a first power rail. A second switch switches a second power voltage and transmits the second power voltage to the common node. A control logic generates a first control signal for controlling the first switch during initial driving of the memory device. A masking circuit controls the first switch to maintain a turn on state in at least a partial period of the initial driving period of the memory device by providing a first masking control signal obtained by masking the first control signal to the first switch.

公开(公告)号：US09275711B2

公开(公告)日：2016-03-01

申请号：US14559623

申请日：2014-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Young Oh

IPC: G11C7/22 ,  G11C8/18 ,  G11C8/10 ,  G11C11/4096 ,  G11C11/4076

CPC classification number: G11C8/18 ,  G11C7/08 ,  G11C7/222 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4096

Abstract: A command processing circuit of a memory device includes a clock divider, a clock controller and a command decoder. The clock divider generates a plurality of divided clock signals based on an external clock signal having a first frequency. The divided clock signals have a second frequency lower than the first frequency. Each of the divided clock signals has a phase that is different from phases of the other divided clock signals. The clock controller generates an operating clock signal based on a command signal and the divided clock signals, where the command signal is transferred in synchronization with the external clock signal. The operating clock signal has the second frequency and a phase corresponding to reception timing of the command signal. The command decoder decodes the command signal in synchronization with the operating clock signal.

Abstract translation: 存储器件的命令处理电路包括时钟分频器，时钟控制器和命令解码器。 时钟分频器基于具有第一频率的外部时钟信号产生多个分频时钟信号。 分频时钟信号具有比第一频率低的第二频率。 每个分频时钟信号具有与其它分频时钟信号的相位不同的相位。 时钟控制器基于命令信号和分配的时钟信号产生操作时钟信号，其中命令信号与外部时钟信号同步地传送。 操作时钟信号具有与指令信号的接收定时对应的第二频率和相位。 命令解码器与操作时钟信号同步地解码命令信号。

公开(公告)号：US10930330B2

公开(公告)日：2021-02-23

申请号：US16717742

申请日：2019-12-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun Shin ,  Tae-Young Oh

IPC: G11C8/06 ,  G11C8/18 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4076 ,  G06F13/16

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US10529407B2

公开(公告)日：2020-01-07

申请号：US16039400

申请日：2018-07-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hwa Kim ,  Tae-Young Oh ,  Jin-Hun Jang ,  Seok-Jin Cho ,  Kyung-Soo Ha

IPC: G11C5/14 ,  G11C11/4074

Abstract: A memory device has a plurality of power rails, including: a first power rail for transmitting a high power voltage, a second power rail for transmitting a low power voltage, a third power rail for selectively receiving the high power voltage from the first power rail through a first dynamic voltage and frequency scaling (DVFS) switch and for selectively receiving the low power voltage from the second power rail through a second DVFS switch, a fourth power rail connected to a first power gating (PG) switch to selectively receive the high power voltage or the low power voltage from the third power rail, and a first circuit block connected to the fourth power rail to receive a power voltage to which the DVFS and PG are applied. When power gating is applied, supply of the power voltage to the fourth power rail is blocked.

公开(公告)号：US10115448B2

公开(公告)日：2018-10-30

申请号：US15194784

申请日：2016-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Ho Lee ,  Seung-Jun Shin ,  Tae-Young Oh

IPC: G11C11/406 ,  G06F3/06

Abstract: A memory device includes a memory bank including a plurality of memory blocks, a row selection circuit and a refresh controller. The row selection circuit is configured to perform an access operation and a refresh operation with respect to the memory bank. The refresh controller is configured to control the row selection circuit such that the memory device is operated selectively in an access mode or a self-refresh mode in response to a self-refresh command received from a memory controller, the refresh operation is performed in the access mode in response to an active command received from the memory controller and the refresh operation is performed in the self-refresh mode in response to at least one clock signal.

公开(公告)号：US10114548B2

公开(公告)日：2018-10-30

申请号：US15690379

申请日：2017-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun Shin ,  Tae-Young Oh

IPC: G06F3/06 ,  G11C8/10 ,  G11C7/10 ,  G11C8/18 ,  G11C7/22 ,  G11C8/06 ,  G11C11/4076

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.