公开(公告)号：US20210065805A1

公开(公告)日：2021-03-04

申请号：US16851622

申请日：2020-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk CHOI ,  Jae-Duk Yu ,  Kang-Bin Lee ,  Sang-Won Shim ,  Bongsoon Lim

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/04 ,  G11C7/10 ,  G11C7/22

Abstract: Each of memory blocks of a nonvolatile memory device includes first memory cells of a first portion of pillar and second memory cells of a second portion of the pillar. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary.

公开(公告)号：US20240290401A1

公开(公告)日：2024-08-29

申请号：US18385185

申请日：2023-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yohan LEE ,  Jaeduk YU ,  Sangsoo PARK ,  Yonghyuk CHOI

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/345 ,  G11C16/0433 ,  G11C16/08

Abstract: A method of controlling a nonvolatile memory device, includes: determining, based on a write address, whether selected memory cells of the nonvolatile memory device corresponding to the write address are included in an over-erased group; based on the selected memory cells being included in the over-erased group, performing a preprogram operation to increase threshold voltages of an over-erased state of the selected memory cells; and after completion of the preprogram operation, performing a data program operation to store write data in the selected memory cells.

公开(公告)号：US20240203509A1

公开(公告)日：2024-06-20

申请号：US18242232

申请日：2023-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungbum KIM ,  Yonghyuk CHOI ,  Hyun SEO ,  Seungyong CHOI

IPC: G11C16/26 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C16/10 ,  G11C16/0483

Abstract: A memory device comprises: a memory cell array including a plurality of cell blocks including a first cell block storing information other than user data and a second cell block storing the user data, wherein each of the plurality of cell blocks includes a plurality of cell strings and control circuitry configured to control a write operation and a read operation of the memory cell array. A first ground select line (GSL) region included in the first cell block includes a plurality of GSLs stacked in a vertical direction. One or more ground select transistors of a plurality of ground select transistors connected to each of the GSLs are programmed to a first threshold voltage and the other ground select transistors of the plurality of ground select transistors not connected to the GSLs are programmed to a second threshold voltage that is higher than the first threshold voltage. A first line included in the first GSL region in the first cell block is arranged at a same height as a word line connected to memory cells storing the user data in the second cell block.

公开(公告)号：US20220075565A1

公开(公告)日：2022-03-10

申请号：US17455037

申请日：2021-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk CHOI ,  Jaeduk YU ,  Sangwan NAM ,  Sangwon PARK ,  Daeseok BYEON ,  Bongsoon LIM

IPC: G06F3/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04

Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

公开(公告)号：US20210201982A1

公开(公告)日：2021-07-01

申请号：US16935712

申请日：2020-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk CHOI ,  Sangwan NAM

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/409 ,  G11C5/06 ,  G11C5/02

Abstract: A memory device includes a memory cell array including cell strings, respectively connected between string select lines and ground select lines, and wordlines connected to memory cells, a control logic to generate a first voltage provided to the string select lines, and a second voltage provided to the ground select lines, and to adjust voltage levels of the first and second voltages to control a channel boosting level of the cell strings, and a row decoder to provide a read voltage, a read pass voltage, and the first and second voltages to the memory cell array under control of the control logic. The control logic generates one of the first and second voltage as a pre-pulse voltage. The row decoder provides a third voltage to at least one of the wordlines.

公开(公告)号：US20210064295A1

公开(公告)日：2021-03-04

申请号：US16891457

申请日：2020-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk YU ,  Bongsoon LIM ,  Yonghyuk CHOI

IPC: G06F3/06

Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.