公开(公告)号：US20220157831A1

公开(公告)日：2022-05-19

申请号：US17378317

申请日：2021-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon BAEK ,  Younghwan SON ,  Miram KWON ,  Junyong PARK ,  Jiho LEE

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565

Abstract: Provided is a three-dimensional semiconductor memory device including a first substrate that includes a cell array region and a connection region; first and second electrode layers that are sequentially stacked and spaced apart from each other on the first substrate, and an end portion of the first electrode layer and an end portion of the second electrode layer are offset from each other on the connection region; a first cell contact penetrating the second electrode layer and the first electrode layer such as to be connected to the second electrode layer on the connection region; and a first contact dielectric pattern between the first cell contact and the first electrode layer. The first cell contact includes columnar part that vertically extends from a top surface of the first substrate, and a connection part that laterally protrudes from the columnar part and contacts the second electrode layer.

公开(公告)号：US20220139951A1

公开(公告)日：2022-05-05

申请号：US17352837

申请日：2021-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghwan SON

IPC: H01L27/11582 ,  H01L29/10 ,  H01L23/522 ,  H01L27/11573 ,  H01L27/1157

Abstract: A semiconductor device includes a gate electrode structure, a channel, a division pattern, an insulation pattern structure, a through via, and a support structure. The gate electrode structure is on a substrate, and includes gate electrodes stacked in a first direction perpendicular to the substrate. Each of the gate electrodes extends in a second direction parallel to the substrate. The channel extends through the gate electrode structure. The division pattern is at each of opposite sides of the gate electrode structure in a third direction parallel to the substrate. The insulation pattern structure extends through the gate electrode structure. The through via extends through the insulation pattern structure. The support structure extends through the gate electrode structure between the insulation pattern structure and the division pattern. The support structure includes first and second extension portion extending in the second and third directions, respectively.

公开(公告)号：US20200343259A1

公开(公告)日：2020-10-29

申请号：US16562919

申请日：2019-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhwan KANG ,  Younghwan SON ,  Haemin LEE ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.

公开(公告)号：US20250157959A1

公开(公告)日：2025-05-15

申请号：US18662536

申请日：2024-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon MOON ,  Younghwan SON ,  Sukkang SUNG

IPC: H01L23/00

Abstract: A semiconductor device may include a circuit element wire, a lower wire connected to the circuit element wire, a lower interlayer insulation layer on the lower wire, and a first contact pad penetrating the lower interlayer insulation layer. The first contact pad may include a first portion connected to the lower wire, a second portion including a void on the first portion, and a third portion on the second portion. A maximum width between both outer surfaces of the second portion along a horizontal direction may be larger than a width of the third portion along the horizontal direction.

公开(公告)号：US20250151271A1

公开(公告)日：2025-05-08

申请号：US18675463

申请日：2024-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehoon LEE ,  Bumkyu KANG ,  Sukkang SUNG ,  Younghwan SON

IPC: H10B43/27 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device including a gate stacking structure, a plurality of channel structures, and a separation pattern. The plurality of channel structures including an adjacent channel structure including a first portion having a surface adjacent to the separation pattern and a separation surface spaced apart from the separation pattern. At least one of the gate dielectric layer or the channel layer is on the separation surface and the adjacent surface in the first portion of the adjacent channel structure.

公开(公告)号：US20250017013A1

公开(公告)日：2025-01-09

申请号：US18887445

申请日：2024-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon BAEK ,  Miram KWON ,  Seongjun SEO ,  Younghwan SON

IPC: H10B43/27 ,  H01L27/06 ,  H10B43/40

Abstract: A semiconductor device includes a first substrate, circuit elements, lower interconnection lines, a second substrate, gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction and forming first and second stack structures, channel structures penetrating through the gate electrodes, and first and second contact plugs penetrating through the first and second stack structures, respectively, and connected to the gate electrodes. The first stack structure has first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the first contact plugs, respectively. The second stack structure has second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the second contact plugs, respectively. The first and second pad areas are offset in relation to each other so as not to overlap each other in the first direction.

公开(公告)号：US20210408040A1

公开(公告)日：2021-12-30

申请号：US17473006

申请日：2021-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhwan KANG ,  Younghwan SON ,  Haemin LEE ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11556

Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.

公开(公告)号：US20210151460A1

公开(公告)日：2021-05-20

申请号：US16928306

申请日：2020-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungdong KIM ,  Younghwan SON ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11526

Abstract: A vertical-type nonvolatile memory device including: a substrate including a cell array area and an extension area, the extension area extending in a first direction from the cell array area and including contacts; a channel structure extending in a vertical direction from the substrate; a first stack structure including gate electrode layers and interlayer insulating layers alternately stacked along sidewalls of the channel structure; a plurality of division areas extending in the first direction and dividing the cell array area and the extension area in a second direction perpendicular to the first direction; in the extension area, two insulating layer dams are arranged between two division areas adjacent to each other; a second stack structure including sacrificial layers and interlayer insulating layers alternately stacked on the substrate between the two insulating layer dams; and an electrode pad connected to a first gate electrode layer in the extension area.