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    Methods of fabricating semiconductor package
    11.
    发明授权
    Methods of fabricating semiconductor package 有权

    公开(公告)号：US11328970B2

    公开(公告)日：2022-05-10

    申请号：US16866594

    申请日：2020-05-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Ho Park ,  Jin-Woo Park ,  Jae Gwon Jang ,  Gwang Jae Jeon

    IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/29

    Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer. The methods may also include forming a first insulating layer in the opening and protruding beyond a top surface of the portion of the second barrier layer on the sacrificial layer, a top surface of the first insulating layer being farther from the first barrier layer than the top surface of the portion of the second barrier layer, forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer, mounting a semiconductor chip on the redistribution structure, attaching a second carrier onto the semiconductor chip and removing the first carrier, removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution structure, and forming solder balls, respectively, on the portions of the redistribution structure.

    Method for fabricating semiconductor package
    12.
    发明授权
    Method for fabricating semiconductor package 有权

    公开(公告)号：US11322368B2

    公开(公告)日：2022-05-03

    申请号：US17037003

    申请日：2020-09-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung-Ho Park ,  Jin-Woo Park ,  Seok Hyun Lee ,  Jae Gwon Jang ,  Gwang Jae Jeon

    IPC: H01L21/48 ,  H01L21/52 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498

    Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.

    Semiconductor package
    16.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11373980B2

    公开(公告)日：2022-06-28

    申请号：US16744623

    申请日：2020-01-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong Youn Kim ,  Dong Kyu Kim ,  Jin-Woo Park ,  Min Jun Bae ,  Gwang Jae Jeon

    IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/544

    Abstract: A semiconductor package includes a first semiconductor chip including a first surface and a second surface which face each other, an alignment pattern formed on the first surface, a first redistribution layer arranged on the first surface of the first semiconductor chip, a second redistribution layer arranged on the second surface of the first semiconductor chip, and electrically connected with the semiconductor chip, and a first dielectric layer including the alignment pattern between the first redistribution layer and the semiconductor chip, the alignment pattern overlapping the first surface of the first semiconductor chip.

    Semiconductor package
    17.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11121064B2

    公开(公告)日：2021-09-14

    申请号：US16819318

    申请日：2020-03-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Ho Park ,  Da Hye Kim ,  Jin-Woo Park ,  Jae Gwon Jang

    IPC: H01L23/495 ,  H01L23/498 ,  H01L23/31

    Abstract: A semiconductor package having a redistribution structure including a first face and a second face and a first semiconductor chip mounted on the first face. The semiconductor package may further include a first redistribution pad exposed from the second face of the redistribution structure and a second redistribution pad exposed from the second face of the redistribution structure. The semiconductor package may further include a first solder ball being in contact with the first redistribution pad and a second solder ball being in contact with the second redistribution pad. In some embodiments, a first distance of the first redistribution pad is smaller than a second distance of the second redistribution pad, the first and second distances are measured with respect to a reference plane that intersects a lower portion of the first solder ball and a lower portion of the second solder ball.

    SEMICONDUCTOR PACKAGE
    18.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210020608A1

    公开(公告)日：2021-01-21

    申请号：US16744623

    申请日：2020-01-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong Youn KIM ,  Dong Kyu Kim ,  Jin-Woo Park ,  Min Jun Bae ,  Gwang Jae Jeon

    IPC: H01L25/065 ,  H01L23/31 ,  H01L23/544 ,  H01L23/00

    Abstract: A semiconductor package includes a first semiconductor chip including a first surface and a second surface which face each other, an alignment pattern formed on the first surface, a first redistribution layer arranged on the first surface of the first semiconductor chip, a second redistribution layer arranged on the second surface of the first semiconductor chip, and electrically connected with the semiconductor chip, and a first dielectric layer including the alignment pattern between the first redistribution layer and the semiconductor chip, the alignment pattern overlapping the first surface of the first semiconductor chip.

    X-ray detector and X-ray imaging apparatus having the same
    20.
    发明授权
    X-ray detector and X-ray imaging apparatus having the same 有权

    公开(公告)号：US10379437B2

    公开(公告)日：2019-08-13

    申请号：US14953064

    申请日：2015-11-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young Ik Kim ,  Jin-Woo Park ,  Eun Jeong Jo

    IPC: G01T1/24 ,  G03B42/02 ,  G01T1/20

    Abstract: Disclosed herein is an X-ray imaging apparatus having an improved structure which is configured for preventing an entrance of foreign materials. The X-ray imaging apparatus includes: an X-ray source configured to generate X-rays, and to irradiate the generated X-rays; an X-ray detector configured to detect the irradiated X-rays; and a first frame and a second frame coupled with each other to form an outer appearance of the X-ray detector. The first frame is tightly coupled with the second frame so that no gap exists between the first frame and the second frame in order to prevent a foreign material from entering the inside of the X-ray detector.

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