公开(公告)号：US09343361B2

公开(公告)日：2016-05-17

申请号：US14072777

申请日：2013-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

IPC: H01L21/76 ,  H01L21/326 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L23/525

CPC classification number: H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

公开(公告)号：US08927340B2

公开(公告)日：2015-01-06

申请号：US13772427

申请日：2013-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Woo Park ,  Seok-Hyun Lee ,  Ho-Geon Song

IPC: H01L21/44 ,  H01L21/50 ,  H01L23/00

CPC classification number: H01L21/50 ,  H01L21/568 ,  H01L24/19 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Provided are a double-sided adhesive tape, semiconductor packages, and methods of fabricating the packages. A method of fabricating semiconductor packages includes providing a double-sided adhesive tape on a top surface of a carrier, the double-sided adhesive tape including a first adhesive layer and a second adhesive layer stacked on the first adhesive layer, the first adhesive layer of the double-sided adhesive tape being in contact with the top surface of the carrier, adhering active surfaces of a plurality of semiconductor chips onto the second adhesive layer of the double-sided adhesive tape, separating the first adhesive layer from the second adhesive layer such that the second adhesive layer remains on the active surfaces of the semiconductor chips, patterning the second adhesive layer to form first openings that selectively expose the active surfaces of the semiconductor chips, and forming first conductive components on the second adhesive layer to fill the first openings.

Abstract translation: 提供双面胶带，半导体封装以及制造封装的方法。 制造半导体封装的方法包括在载体的顶表面上提供双面胶带，所述双面胶带包括第一粘合剂层和层叠在第一粘合剂层上的第二粘合剂层，第一粘合剂层 所述双面胶带与所述载体的顶表面接触，将多个半导体芯片的活性表面粘合到所述双面胶带的第二粘合剂层上，从而将所述第一粘合剂层与所​​述第二粘合层分离， 第二粘合剂层保留在半导体芯片的有效表面上，图案化第二粘合剂层以形成选择性地暴露半导体芯片的有效表面的第一开口，以及在第二粘合剂层上形成第一导电部件以填充第一开口 。

公开(公告)号：US20200013753A1

公开(公告)日：2020-01-09

申请号：US16359097

申请日：2019-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-Soo Kim ,  Seung-Duk Baek ,  Sun-Won Kang ,  Ho-Geon Song ,  Gun-Ho Chang

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor chip includes a semiconductor substrate, a through electrode, an inter-mediation pad, an upper pad, and a rewiring line. The semiconductor substrate includes a first surface that is an active surface and a second surface that is opposite to the first surface. The through electrode penetrates the semiconductor substrate and is disposed in at least one column in a first direction in a center portion of the semiconductor substrate. The inter-mediation pad is disposed in at least one column in the first direction in an edge portion of the second surface. The upper pad is disposed on the second surface and connected to the through electrode. The rewiring line is disposed on the second surface and connects the inter-mediation pad to the upper pad.

公开(公告)号：US20130328177A1

公开(公告)日：2013-12-12

申请号：US13771609

申请日：2013-02-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun-Rae Cho ,  Tae-Hoon Kim ,  Ho-Geon Song ,  Seok-Won Lee

IPC: H01L21/56 ,  H01L23/552

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

Abstract translation: 为了制造堆叠半导体封装，板模具覆盖第一半导体。 板模具包括第一面和与第一面相对的第二面。 第一半导体的有源表面面向第二面。 第一开口从第二表面形成在板模具中。 第一开口设置在第一半导体上。 第二开口从第一表面穿透板模。 导电金属层使用化学镀方法填充第一和第二开口。 多个半导体器件堆叠在基板模具的第一面上。

公开(公告)号：US09099460B2

公开(公告)日：2015-08-04

申请号：US14466207

申请日：2014-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun-Rae Cho ,  Tae-Hoon Kim ,  Ho-Geon Song ,  Seok-Won Lee

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/552 ,  H01L23/28 ,  H01L23/31 ,  H01L23/00 ,  H01L25/03 ,  H01L25/18 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

Abstract translation: 为了制造堆叠半导体封装，板模具覆盖第一半导体。 板模具包括第一面和与第一面相对的第二面。 第一半导体的有源表面面向第二面。 第一开口从第二表面形成在板模具中。 第一开口设置在第一半导体上。 第二开口从第一表面穿透板模。 导电金属层使用化学镀方法填充第一和第二开口。 多个半导体器件堆叠在基板模具的第一面上。

公开(公告)号：US10756062B2

公开(公告)日：2020-08-25

申请号：US16359097

申请日：2019-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-Soo Kim ,  Seung-Duk Baek ,  Sun-Won Kang ,  Ho-Geon Song ,  Gun-Ho Chang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor chip includes a semiconductor substrate, a through electrode, an inter-mediation pad, an upper pad, and a rewiring line. The semiconductor substrate includes a first surface that is an active surface and a second surface that is opposite to the first surface. The through electrode penetrates the semiconductor substrate and is disposed in at least one column in a first direction in a center portion of the semiconductor substrate. The inter-mediation pad is disposed in at least one column in the first direction in an edge portion of the second surface. The upper pad is disposed on the second surface and connected to the through electrode. The rewiring line is disposed on the second surface and connects the inter-mediation pad to the upper pad.

公开(公告)号：US20140363923A1

公开(公告)日：2014-12-11

申请号：US14466207

申请日：2014-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun-Rae Cho ,  Tae-Hoon Kim ,  Ho-Geon Song ,  Seok-Won Lee

IPC: H01L25/00 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

Abstract translation: 为了制造堆叠半导体封装，板模具覆盖第一半导体。 板模具包括第一面和与第一面相对的第二面。 第一半导体的有源表面面向第二面。 第一开口从第二表面形成在板模具中。 第一开口设置在第一半导体上。 第二开口从第一表面穿透板模。 导电金属层使用化学镀方法填充第一和第二开口。 多个半导体器件堆叠在基板模具的第一面上。

公开(公告)号：US08890294B2

公开(公告)日：2014-11-18

申请号：US13771609

申请日：2013-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae Cho ,  Tae-Hoon Kim ,  Ho-Geon Song ,  Seok-Won Lee

IPC: H01L23/522 ,  H01L21/56 ,  H01L23/552 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

Abstract translation: 为了制造堆叠半导体封装，板模具覆盖第一半导体。 板模具包括第一面和与第一面相对的第二面。 第一半导体的有源表面面向第二面。 第一开口从第二表面形成在板模具中。 第一开口设置在第一半导体上。 第二开口从第一表面穿透板模。 导电金属层使用化学镀方法填充第一和第二开口。 多个半导体器件堆叠在基板模具的第一面上。