公开(公告)号：US10885954B2

公开(公告)日：2021-01-05

申请号：US15840601

申请日：2017-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yeop Baeck ,  Inhak Lee ,  SangShin Han ,  Tae-Hyung Kim ,  JaeSeung Choi ,  Sunghyun Park ,  Hyunsu Choi

IPC: G11C7/10 ,  G11C11/419 ,  G11C11/4096 ,  G11C7/12 ,  G11C5/14 ,  G11C8/08 ,  G11C8/16 ,  G11C11/412

Abstract: A memory device includes a first write assist circuit providing a cell voltage or a write assist voltage to a first memory cell connected with a first bit line pair, a first write driver that provides write data to the first memory cell through the first bit line pair, a second write assist circuit that provides the cell voltage or the write assist voltage to a second memory cell connected with a second bit line pair, and a second write driver that provides write data to the second memory cell through the second bit line pair. One of the first and second write assist circuits provides the write assist voltage in response to a column selection signal for selecting one write driver, which provides write data, from among the first, and second write drivers, and the other thereof provides the cell voltage in response to the column selection signal.

公开(公告)号：US09916120B2

公开(公告)日：2018-03-13

申请号：US15045485

申请日：2016-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Hyung Kim ,  Kwang-Hyun Ko ,  Alexander Larionov ,  Yong-Ha Choi

IPC: G06F3/14

CPC classification number: G06F3/1431 ,  G06F3/1454

Abstract: A method and an electronic device for providing a screen mirroring service are provided. The method includes connecting a control channel to at least one other electronic device when an electronic device executes a screen mirroring service, transmitting screen data comprising an added virtual key, to the other electronic device, and performing a function based on a control signal corresponding to using the virtual key received from the other electronic device over the control channel.

公开(公告)号：US09812220B2

公开(公告)日：2017-11-07

申请号：US15207557

申请日：2016-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Hyung Kim ,  Huichong Shin ,  Seokil Kim ,  Young Yun ,  Jonghyoung Lim ,  Youkeun Han

IPC: G11C7/10 ,  G11C29/34 ,  G06F3/06 ,  G06F12/1009 ,  G11C11/4076 ,  G11C11/4093 ,  G11C5/04

CPC classification number: G11C29/34 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0868 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1024 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/06 ,  G11C29/26 ,  G11C2029/0407

Abstract: A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.

公开(公告)号：US20240321344A1

公开(公告)日：2024-09-26

申请号：US18612372

申请日：2024-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hyun Choi ,  Ho Young Tang ,  Eo Jin Lee ,  Tae-Hyung Kim ,  Yu Tak Jeong

IPC: G11C11/412 ,  G11C11/419 ,  H01L23/528 ,  H10B10/00

CPC classification number: G11C11/412 ,  H01L23/528 ,  H10B10/12 ,  G11C11/419

Abstract: A memory device is provided. The memory device includes a memory cell array including a plurality of memory cells arranged in a plurality of columns and rows and including first and second memory cells in a same column and different rows, the plurality of columns intersecting the plurality of rows in a plan view, a first bit line transistor electrically connected between the first memory cell and a first bit line metal line and a second bit line transistor electrically connected between the second memory cell and a second bit line metal line, wherein the first bit line metal line is on an upper surface of the memory cell array, and the second bit line metal line is on a lower surface of the memory cell array opposite the upper surface of the memory cell array.

公开(公告)号：US11854610B2

公开(公告)日：2023-12-26

申请号：US18164199

申请日：2023-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop Baeck ,  Tae-Hyung Kim ,  Daeyoung Moon ,  Dong-Wook Seo ,  Inhak Lee ,  Hyunsu Choi ,  Taejoong Song ,  Jae-Seung Choi ,  Jung-Myung Kang ,  Hoon Kim ,  Jisu Yu ,  Sun-Yung Jang

IPC: G11C11/419 ,  H10B10/00 ,  G11C7/08 ,  H01L23/528 ,  H01L27/092

CPC classification number: G11C11/419 ,  G11C7/08 ,  H01L23/5286 ,  H01L27/092 ,  H10B10/12 ,  H10B10/18

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US11581038B2

公开(公告)日：2023-02-14

申请号：US17412588

申请日：2021-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop Baeck ,  Tae-Hyung Kim ,  Daeyoung Moon ,  Dong-Wook Seo ,  Inhak Lee ,  Hyunsu Choi ,  Taejoong Song ,  Jae-Seung Choi ,  Jung-Myung Kang ,  Hoon Kim ,  Jisu Yu ,  Sun-Yung Jang

IPC: G11C11/419 ,  G11C7/08 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US20180294018A1

公开(公告)日：2018-10-11

申请号：US15840601

申请日：2017-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yeop Baeck ,  Inhak Lee ,  SangShin Han ,  Tae-Hyung Kim ,  JaeSeung Choi ,  Sunghyun Park ,  Hyunsu Choi

IPC: G11C7/10 ,  G11C11/419 ,  G11C11/4096 ,  G11C7/12 ,  G11C11/412 ,  G11C5/14 ,  G11C8/08 ,  G11C8/16

Abstract: A memory device includes a first write assist circuit providing a cell voltage or a write assist voltage to a first memory cell connected with a first bit line pair, a first write driver that provides write data to the first memory cell through the first bit line pair, a second write assist circuit that provides the cell voltage or the write assist voltage to a second memory cell connected with a second bit line pair, and a second write driver that provides write data to the second memory cell through the second bit line pair. One of the first and second write assist circuits provides the write assist voltage in response to a column selection signal for selecting one write driver, which provides write data, from among the first, and second write drivers, and the other thereof provides the cell voltage in response to the column selection signal.

公开(公告)号：US09407895B2

公开(公告)日：2016-08-02

申请号：US14011085

申请日：2013-08-27

Applicant: Samsung Electronics Co. Ltd.

Inventor： You-Kyung Cho ,  Soung-Kwan Kimn ,  Jong-Kyu Kim ,  Tae-Hyung Kim ,  Jung-Wook Chai

IPC: H04N9/80 ,  H04N9/87 ,  H04N21/414 ,  H04N21/63 ,  H04N5/765 ,  H04N5/783

CPC classification number: H04N9/87 ,  H04N5/765 ,  H04N5/783 ,  H04N21/41407 ,  H04N21/632

Abstract: A system for controlling a video is provided. The system includes a terminal which transmits a flush command to an external device to delete buffered data in a buffer of the external device when a search command for moving to a location of specific data of a video is generated while data of the video is streamed to the external device and which then transmits to the external device the specific data located in relation to the search command, and an external device which deletes the buffered data in the buffer when the flush command is received from the terminal while a video streamed from the terminal is reproduced and which buffers the specific data of the video received from the terminal in the buffer to be output.

Abstract translation: 提供了一种用于控制视频的系统。 该系统包括一个终端，当用于移动到视频的特定数据的位置的搜索命令生成视频的数据，同时将视频的数据流传输到外部设备的缓冲器中时，向外部设备发送刷新命令以删除外部设备的缓冲器中的缓冲数据， 外部设备，然后向外部设备发送与搜索命令相关的特定数据;以及外部设备，当从终端接收到视频流时，从终端接收到刷新命令时，删除缓冲器中的缓冲数据 被再现并且缓冲从缓冲器中的终端接收的视频的特定数据以被输出。