公开(公告)号：US11296113B2

公开(公告)日：2022-04-05

申请号：US17007761

申请日：2020-08-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kwang-Ho Kim ,  Peter Rabkin

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L23/522 ,  H01L27/1157 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11565 ,  H01L27/11556

Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

公开(公告)号：US11270963B2

公开(公告)日：2022-03-08

申请号：US16742213

申请日：2020-01-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen Wu ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L23/00 ,  H01L25/18 ,  H01L27/11556 ,  H01L27/11526 ,  H01L25/00

Abstract: A semiconductor die includes a first pad-level dielectric layer embedding first bonding pads and located over a first substrate. Each of the first bonding pads is located within a respective pad cavity in the first pad-level dielectric layer. Each of the first bonding pads includes a first metallic liner containing a first metallic liner material and contacting a sidewall of the respective pad cavity, a first metallic fill material portion embedded in the first metallic liner, and a metallic electromigration barrier layer contacting the first metallic fill material portion and adjoined to the first metallic liner.

公开(公告)号：US11031088B2

公开(公告)日：2021-06-08

申请号：US16909830

申请日：2020-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dae Wung Kang ,  Peter Rabkin ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C7/04 ,  G11C16/04 ,  G11C11/4074 ,  G11C11/56

Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory over a wide range of operating temperatures are described. The amount of shifting in the threshold voltages of memory cell transistors over temperature may depend on the location of the memory cell transistors within a NAND string. To compensate for these variations, the threshold voltages of memory cell transistors in the middle of the NAND string or associated with a range of word lines between the ends of the NAND string may be adjusted by increasing the word line voltages biasing memory cell transistors on the drain-side of the selected word line when the read temperature is greater than a first threshold temperature and/or decreasing the word line voltages biasing memory cell transistors on the source-side of the selected word line when the read temperature is less than a second threshold temperature.

公开(公告)号：US10789992B2

公开(公告)日：2020-09-29

申请号：US16168168

申请日：2018-10-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luisa Lin ,  Mohan Dunga ,  Venkatesh P. Ramachandra ,  Peter Rabkin ,  Masaaki Higashitani

IPC: G11C11/24 ,  G11C5/06 ,  H01L27/1157 ,  H01L27/11573 ,  G11C16/08 ,  G11C5/10 ,  G11C16/28 ,  G11C16/24 ,  H01L27/11578

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the I/O pads.

公开(公告)号：US10726926B2

公开(公告)日：2020-07-28

申请号：US16248000

申请日：2019-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dae Wung Kang ,  Peter Rabkin ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C7/04 ,  G11C16/04 ,  G11C11/4074 ,  G11C11/56

Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory over a wide range of operating temperatures are described. The amount of shifting in the threshold voltages of memory cell transistors over temperature may depend on the location of the memory cell transistors within a NAND string. To compensate for these variations, the threshold voltages of memory cell transistors in the middle of the NAND string or associated with a range of word lines between the ends of the NAND string may be adjusted by increasing the word line voltages biasing memory cell transistors on the drain-side of the selected word line when the read temperature is greater than a first threshold temperature and/or decreasing the word line voltages biasing memory cell transistors on the source-side of the selected word line when the read temperature is less than a second threshold temperature.

公开(公告)号：US20200105349A1

公开(公告)日：2020-04-02

申请号：US16248000

申请日：2019-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dae Wung Kang ,  Peter Rabkin ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C7/04 ,  G11C11/56 ,  G11C11/4074 ,  G11C16/04

Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory over a wide range of operating temperatures are described. The amount of shifting in the threshold voltages of memory cell transistors over temperature may depend on the location of the memory cell transistors within a NAND string. To compensate for these variations, the threshold voltages of memory cell transistors in the middle of the NAND string or associated with a range of word lines between the ends of the NAND string may be adjusted by increasing the word line voltages biasing memory cell transistors on the drain-side of the selected word line when the read temperature is greater than a first threshold temperature and/or decreasing the word line voltages biasing memory cell transistors on the source-side of the selected word line when the read temperature is less than a second threshold temperature.

公开(公告)号：US09818801B1

公开(公告)日：2017-11-14

申请号：US15293971

申请日：2016-10-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Perumal Ratnam ,  Christopher J. Petti ,  Masaaki Higashitani

IPC: H01L27/115 ,  H01L45/00 ,  H01L29/778 ,  H01L27/24 ,  H01L23/528 ,  H01L29/205 ,  H01L29/12 ,  H01L29/66 ,  H01L27/11582 ,  H01L29/78

CPC classification number: H01L27/2481 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/2409 ,  H01L29/122 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7833 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608

Abstract: A three-dimensional resistive memory device includes an alternating stack of electrically conductive layers and insulating layers. Resistive memory elements are provided between the electrically conductive layers and a semiconductor local bit line. The semiconductor local bit line includes a heterostructure of an inner semiconductor material layer having an inner-material band gap and an outer semiconductor material layer having an outer-material band gap that is narrower than the inner-material band. A gate dielectric is located between a gate electrode and the inner semiconductor material layer.

公开(公告)号：US12219756B2

公开(公告)日：2025-02-04

申请号：US17664550

申请日：2022-05-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani

IPC: H10B41/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device includes at least one instance of a unit layer stack including a source layer, a channel-containing layer that contains a semiconductor channel, and a drain layer that are stacked along a vertical direction over a substrate; a memory opening vertically extending through the at least one instance of the unit layer stack; and a memory opening fill structure located in the memory opening and including a control gate electrode and a memory film in contact with each instance of the semiconductor channel. The memory film includes a resonant tunneling barrier stack, a barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the barrier layer.

公开(公告)号：US11963352B2

公开(公告)日：2024-04-16

申请号：US17362034

申请日：2021-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani

IPC: H10B43/27 ,  H01L21/02 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L29/24 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L21/02565 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L29/24 ,  H10B41/27 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1067 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom electrode, a metal oxide semiconductor vertical transistor channel, a cylindrical gate dielectric, and a top electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

公开(公告)号：US11948902B2

公开(公告)日：2024-04-02

申请号：US17370317

申请日：2021-07-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin Hou ,  Peter Rabkin ,  Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Masaaki Higashitani

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/03 ,  H01L2224/0225 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/08146 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads laterally surrounded by a first pad-level dielectric layer. The first pad-level dielectric layer includes at least one first encapsulated airgap located between neighboring pairs of first bonding pads and encapsulated by a first dielectric fill material of the first pad-level dielectric layer. The bonded assembly includes a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads laterally surrounded by a second pad-level dielectric layer. Each of the second bonding pads is bonded to a respective one of the first bonding pads.