公开(公告)号：US12027218B2

公开(公告)日：2024-07-02

申请号：US17554321

申请日：2021-12-17

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Prafful Golani ,  Ravi Kumar

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

Abstract: A method for performing a program verify operation with respect to a target memory cell in a memory structure of a non-volatile memory system is provided. The method may include the step of determining a location of the target memory cell within the structure and, based upon the determined location of the target cell and with respect to each programmable memory state: (1) applying a first sense signal at a first point in time, and (2) applying a second sense signal at a second point in time. A time interval between the first and the second points in time is equal to a predetermined optimal time period plus or minus an offset parameter time value.

公开(公告)号：US11972814B2

公开(公告)日：2024-04-30

申请号：US17701320

申请日：2022-03-22

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Yu-Chung Lien ,  Ravi Kumar ,  Jiahui Yuan ,  Bo Lei ,  Zhenni Wan

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

Abstract: The memory device includes a plurality of memory cells, which include a first set of memory cells and a second set of memory cells. A controller is in communication with the memory cells. The controller is configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states. The controller is further configured to, in the first programming pass, verify the first set of memory cells at a first set of checkpoint data states and verify the second set of memory cells at a second set of checkpoint data states that is different than the first set of checkpoint data states.

公开(公告)号：US20230253048A1

公开(公告)日：2023-08-10

申请号：US17667100

申请日：2022-02-08

Applicant: SanDisk Technologies LLC

Inventor： Sujjatul Islam ,  Ravi Kumar

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/32

CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/32 ,  G11C16/0483 ,  G11C16/3459 ,  H01L27/11556

Abstract: The memory device includes an array of memory cells, which are configured to retain multiple bits per memory cell, arranged in a plurality of word lines. A controller is configured to program the memory cells of a selected word line in a first programming pass. The first programming pass includes a plurality of programming pulses, each including the application of a programming voltage Vpgm by the controller to a control gate of the selected word line for a first duration. The controller is also configured to further program the memory cells of the selected word line in a second programming pass. The second programming pass includes a plurality of programming pulses, each of which includes the application of a programming voltage Vpgm by the controller to the control gate of the selected word line for a second duration that is different than the first duration.

公开(公告)号：US11699494B2

公开(公告)日：2023-07-11

申请号：US17340826

申请日：2021-06-07

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Yu-Chung Lien ,  Deepanshu Dutta ,  Huai-yuan Tseng ,  Ravi Kumar

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C2216/16

Abstract: A method for programming a memory block of a non-volatile memory structure, wherein the method provides, during a program verify operation, selecting only a partial segment of memory cells of a memory block for bit scan mode, applying a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells, and initiating a bit scan mode of the selected memory cells.

公开(公告)号：US11568943B2

公开(公告)日：2023-01-31

申请号：US17102954

申请日：2020-11-24

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Dengtao Zhao ,  Deepanshu Dutta ,  Ravi Kumar

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/08 ,  G11C16/14

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines and are also arranged in strings and configured to retain a threshold voltage within a common range of threshold voltages. A control circuit coupled to the plurality of word lines and the strings is configured to determine an erase upper tail voltage of a distribution of the threshold voltage of the memory cells following an erase operation. The erase upper tail voltage corresponds to a cycling condition of the memory cells. The control circuit is also configured to calculate a program voltage to apply to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells during a program operation based on the erase upper tail voltage.

公开(公告)号：US11557358B2

公开(公告)日：2023-01-17

申请号：US17231071

申请日：2021-04-15

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Deepanshu Dutta ,  Ravi Kumar

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in strings and configured to retain a threshold voltage. Each of the memory cells is configured to be erased in an erase operation occurring during an erase time period. A control circuit is configured to adjust at least a portion of the erase time period in response to determining the erase operation is a segmented erase operation and is resumed after being suspended. The control circuit applies an erase signal having a plurality of voltage segments temporally separated from one another during the erase time period to each of the strings while simultaneously applying a word line erase voltage to selected ones of the word lines to encourage erasing of the memory cells coupled to the selected ones of the word lines in the segmented erase operation.

公开(公告)号：US11508440B1

公开(公告)日：2022-11-22

申请号：US17323708

申请日：2021-05-18

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Ravi Kumar ,  Chin-Yi Chen ,  Ryohei Shoji

IPC: G11C16/24 ,  G11C16/10 ,  G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  H01L27/11582

Abstract: A nonvolatile memory control method includes a step of writing, repeatedly to a nonvolatile memory cells. The method continues with detecting when writing reaches a writing threshold value. Upon reaching the writing threshold, the method continues with driving a charge to at least one parasitic area intermediate at least two charge storage areas of the nonvolatile memory cells to improve data retention in at least one of the at least two charge storage areas of the nonvolatile memory cells.

公开(公告)号：US20220336029A1

公开(公告)日：2022-10-20

申请号：US17231071

申请日：2021-04-15

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Deepanshu Dutta ,  Ravi Kumar

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/16

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in strings and configured to retain a threshold voltage. Each of the memory cells is configured to be erased in an erase operation occurring during an erase time period. A control circuit is configured to adjust at least a portion of the erase time period in response to determining the erase operation is a segmented erase operation and is resumed after being suspended. The control circuit applies an erase signal having a plurality of voltage segments temporally separated from one another during the erase time period to each of the strings while simultaneously applying a word line erase voltage to selected ones of the word lines to encourage erasing of the memory cells coupled to the selected ones of the word lines in the segmented erase operation.

公开(公告)号：US11475967B1

公开(公告)日：2022-10-18

申请号：US17307626

申请日：2021-05-04

Applicant: SanDisk Technologies LLC

Inventor： Xue Pitner ,  Muhammad Masuduzzaman ,  Ravi Kumar

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  H01L27/11565 ,  G11C11/56 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519

Abstract: The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged word lines. The control circuitry is configured to program the memory cells using a multi-pass programming operation which includes a first pass and a second pass. The first pass programs the memory cells to a first number of data states, and the second pass programs the memory cells to a greater second number of data states. For at least one word line, during the second pass, a voltage that is applied to at least one memory cell is reduced from a verify voltage by an offset which is determined as a function of a data state of an adjacent memory cell of an adjacent word line and wherein the first pass but not the second pass has been completed in the adjacent word line.

公开(公告)号：US11302409B2

公开(公告)日：2022-04-12

申请号：US16854030

申请日：2020-04-21

Applicant: SanDisk Technologies LLC

Inventor： Xue Pitner ,  Deepanshu Dutta ,  Huai-Yuan Tseng ,  Ravi Kumar ,  Cynthia Hsu

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to program memory cells of a plurality of strings of a word line of the block and verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, where each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line. Further, the circuit is configured to determine a number of sets of the plurality of memory cell sets that are verified to be in a first data state and determine, based on the number of sets, whether the block is faulty.