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    Block configuration for memory device with separate sub-blocks
    13.
    发明授权
    Block configuration for memory device with separate sub-blocks 有权

    公开(公告)号：US11587619B2

    公开(公告)日：2023-02-21

    申请号：US17360677

    申请日：2021-06-28

    Applicant: SanDisk Technologies LLC

    Inventor： Yu-Chung Lien ,  Jiahui Yuan ,  Deepanshu Dutta

    IPC: G11C11/00 ,  G11C16/08 ,  G11C16/04

    Abstract: A memory device is provided in which blocks of memory cells are divided into separate portions or sub-blocks with respective sets of word line switching transistors. The sub-blocks can be arranged on a substrate on opposite sides of a dividing line, where a separate set of bit lines is provided on each side of the dividing line. Each block has a row decoder which provides a common word line voltage signal to each sub-block of the block. However, each sub-block can have an independent set of word line switching transistors so that the common word line voltage signal can be passed or blocked independently for each sub-block. The blocks of memory cells can be provided on a first die which is inverted and bonded to a second die which includes the sets of word line switching transistors.

    MULTI-LEVEL PROGRAM PULSE FOR PROGRAMMING SINGLE LEVEL MEMORY CELLS TO REDUCE DAMAGE
    14.
    发明申请
    MULTI-LEVEL PROGRAM PULSE FOR PROGRAMMING SINGLE LEVEL MEMORY CELLS TO REDUCE DAMAGE 有权

    公开(公告)号：US20220328112A1

    公开(公告)日：2022-10-13

    申请号：US17229705

    申请日：2021-04-13

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Jiahui Yuan ,  Abhijith Prakash

    IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30 ,  G11C16/08

    Abstract: Apparatuses and techniques are described for reducing damage to memory cells during single bit per cell programming. An initial program pulse in a single bit per cell program operation has a lower, first program level followed by a higher, second program level. As a result of the lower, first program level, the electric field across the memory cells is reduced. The step up time from the first program level to the second program level can be reduced by concurrently stepping up pass voltages of the adjacent unselected word lines. If an additional program pulse is applied, the step up in the program pulse can be omitted. The magnitude of the first program level can be adjusted based on factors such as temperature, number of program-erase cycles, selected sub-block position and selected word line position.

    Refresh operations for dedicated groups of blocks of memory cells
    15.
    发明授权
    Refresh operations for dedicated groups of blocks of memory cells 有权

    公开(公告)号：US11043280B1

    公开(公告)日：2021-06-22

    申请号：US16790306

    申请日：2020-02-13

    Applicant: SanDisk Technologies LLC

    Inventor： Abhijith Prakash ,  Jiahui Yuan

    IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/26 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/11556

    Abstract: Apparatuses and techniques are described for periodically refreshing word line voltages in a group of blocks in a memory device. In one aspect, each group of blocks stores the same number of bits per cell. For example, one group of blocks can be reserved for single level cell (SLC) data and another group of blocks can be reserved for multi-level cell (MLC) data. A common refresh voltage signal can be applied to the blocks in a group, where the voltage signal is optimized based on the number of bits per cell stored by the memory cells of the group. For an SLC block, the refresh voltage signal can decrease a floating voltage of the word lines. For an MLC block, the refresh voltage signal can increase a floating voltage of the word lines.

    Temperature and cycling dependent refresh operation for memory cells
    16.
    发明授权
    Temperature and cycling dependent refresh operation for memory cells 有权

    公开(公告)号：US11037641B1

    公开(公告)日：2021-06-15

    申请号：US16704817

    申请日：2019-12-05

    Applicant: SanDisk Technologies LLC

    Inventor： Abhijith Prakash ,  Vishwanath Basavaegowda Shanthakumar ,  Jiahui Yuan

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  H01L27/11582 ,  H01L27/11556

    Abstract: Apparatuses and techniques are described for periodically refreshing word line voltages in a memory device. A decision to perform a refresh operation is made based on the temperature and number of program-erase (P-E) cycles. In one approach, the refresh operation is not performed if the number of P-E cycles is below a threshold number and/or the temperature is below a threshold temperature. When the temperature and number of P-E cycles indicate that a refresh operation should be performed, a timer counts an elapsed time until the elapsed time reaches an allowed discharge time. The allowed discharge time can be based on the temperature, number of P-E cycles, and other factors which affect an expected number of fail bits. The allowed discharge time can also change as the temperature changes during the counting of the elapsed time.

    TEMPERATURE AND CYCLING DEPENDENT REFRESH OPERATION FOR MEMORY CELLS
    17.
    发明申请
    TEMPERATURE AND CYCLING DEPENDENT REFRESH OPERATION FOR MEMORY CELLS 有权

    公开(公告)号：US20210174886A1

    公开(公告)日：2021-06-10

    申请号：US16704817

    申请日：2019-12-05

    Applicant: SanDisk Technologies LLC

    Inventor： Abhijith Prakash ,  Vishwanath Basavaegowda Shanthakumar ,  Jiahui Yuan

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/26

    Abstract: Apparatuses and techniques are described for periodically refreshing word line voltages in a memory device. A decision to perform a refresh operation is made based on the temperature and number of program-erase (P-E) cycles. In one approach, the refresh operation is not performed if the number of P-E cycles is below a threshold number and/or the temperature is below a threshold temperature. When the temperature and number of P-E cycles indicate that a refresh operation should be performed, a timer counts an elapsed time until the elapsed time reaches an allowed discharge time. The allowed discharge time can be based on the temperature, number of P-E cycles, and other factors which affect an expected number of fail bits. The allowed discharge time can also change as the temperature changes during the counting of the elapsed time.

    Early detection of programming failure for non-volatile memory
    19.
    发明授权
    Early detection of programming failure for non-volatile memory 有权

    公开(公告)号：US12148489B2

    公开(公告)日：2024-11-19

    申请号：US17874014

    申请日：2022-07-26

    Applicant: SanDisk Technologies LLC

    Inventor： Yi Song ,  Sarath Puthenthermadam ,  Jiahui Yuan

    IPC: G11C29/12 ,  G11C11/408 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04

    Abstract: An apparatus is provided that includes a block including a word line coupled to a plurality of memory cells, and a control circuit coupled to the word line. The control circuit is configured to program the plurality of memory cells by applying program pulses to the word line in a plurality of program loops, determining a first count of a number of the program loops used to complete programming a first subset of the plurality of memory cells to a first programmed state, first comparing the first count to a corresponding first lower limit and a corresponding first upper limit, and determining whether programming the plurality of memory cells has failed based on a result of the first comparing step.

    NAND string read voltage adjustment
    20.
    发明授权
    NAND string read voltage adjustment 有权

    公开(公告)号：US12105963B2

    公开(公告)日：2024-10-01

    申请号：US17940465

    申请日：2022-09-08

    Applicant: SanDisk Technologies LLC

    Inventor： Yi Song ,  Jiahui Yuan ,  Yanjie Wang

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

    Abstract: An apparatus includes a control circuit configured to connect to NAND strings that are connected to bit lines, where each bit line is connected to a plurality of NAND strings in a corresponding plurality of regions of a block. The control circuit is configured to apply a read voltage in read operations directed to NAND strings of the plurality of regions of the block and subsequently adjust the read voltage by a first predetermined amount for read operations directed to NAND strings of a first region of the block. The control circuit is further configured to adjust the read voltage by a second predetermined amount for read operations directed to NAND strings of a second region of the block. The first and second predetermined amounts are based on respective locations of the first and second regions in the block.

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