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公开(公告)号：US20090113137A1
公开(公告)日：2009-04-30
申请号：US11929180
申请日：2007-10-30
IPC分类号： G06F12/08
CPC分类号： G06F12/128 , G06F12/122
摘要： A multi-way cache system includes multi-way cache storage circuitry, a pseudo least recently used (PLRU) tree state representative of a PLRU tree, the PLRU tree having a plurality of levels, and PLRU control circuitry coupled to the multi-way cache storage circuitry and the PLRU tree state. The PLRU control circuitry has programmable PLRU tree level update enable circuitry which selects Y levels of the plurality of levels of the PLRU tree to be updated. The PLRU control circuitry, in response to an address hitting or resulting in an allocation in the multi-way cache storage circuitry, updates only the selected Y levels of the PLRU tree state.
摘要翻译： 多路缓存系统包括多路缓存存储电路，代表PLRU树的伪最近最少使用（PLRU）树状态，具有多个电平的PLRU树，以及耦合到多路缓存的PLRU控制电路 存储电路和PLRU树状态。 PLRU控制电路具有可编程PLRU树级更新使能电路，其选择要更新的PLRU树的多个级别的Y级。 PLRU控制电路响应于在多路高速缓存存储电路中的分配地址或导致分配，仅更新PLRU树状态的所选Y级。
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12.发明申请TECHNIQUE FOR DETERMINING IF A LOGICAL SUM OF A FIRST OPERAND AND A SECOND OPERAND IS THE SAME AS A THIRD OPERAND 有权如果第一个操作的逻辑关系和第二个操作与第三个操作相同，则用于确定的技术公开(公告)号：US20100306302A1
公开(公告)日：2010-12-02
申请号：US12474451
申请日：2009-05-29
CPC分类号： G06F7/02 , G06F7/48 , G06F12/0864
摘要： A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings.
摘要翻译： 系统用于确定第一操作数和第二操作数的和是否与第三操作数相同，其中与第三操作数的比较具有可变长度。 这在内容可寻址存储器（CAM）中特别有用，其中命中的可能性在集合的关联高速缓存中通常被改善，并允许CAM识别不同的事物。 例如，条目可以是识别存储器的页面的一个长度，而另一个条目是不同的长度以标识存储器页面。 通过参考以下描述和附图可以更好地理解这一点。
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公开(公告)号：US20090037666A1
公开(公告)日：2009-02-05
申请号：US11832797
申请日：2007-08-02
申请人： Syed R. Rahman , David F. Greenberg , Kathryn C. Stacer , Klas M. Bruce , Matt B. Smittle , Michael D. Snyder , Gary L. Whisenhunt
发明人： Syed R. Rahman , David F. Greenberg , Kathryn C. Stacer , Klas M. Bruce , Matt B. Smittle , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/0846 , G06F12/0891
摘要： A method and device for locking a cache line of a cache is disclosed. The method includes automatically changing a state of a cache line from a valid locked state to an invalid locked state in response to receiving an indication that a memory location external to the cache and corresponding to the cache line is associated with an access request by a processor or other data access module. Thus, the locked state of a cache line is maintained even after data in the locked cache line is invalidated. By maintaining the invalid locked state, the cache line is not available for reallocation by the cache. This allows locked cache lines that become invalidated to remain locked without additional software overhead to periodically determine whether the lock has been lost due to invalidation of the cache line.
摘要翻译： 公开了一种用于锁定高速缓存的高速缓存行的方法和设备。 该方法包括响应于接收到高速缓存行外部的对应于高速缓存行的存储器位置与处理器的访问请求相关联的指示，自动将高速缓存行的状态从有效锁定状态改变为无效锁定状态 或其他数据访问模块。 因此，即使在锁定的高速缓存行中的数据无效之后，也保持高速缓存行的锁定状态。 通过保持无效的锁定状态，高速缓存行不可用于高速缓存的重新分配。 这允许被锁定的高速缓存行保持锁定，而不需要额外的软件开销来定期确定锁是否由于高速缓存行的无效而丢失。
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公开(公告)号：US20080282251A1
公开(公告)日：2008-11-13
申请号：US11746998
申请日：2007-05-10
CPC分类号： G06F9/485 , G06F9/3009 , G06F9/3013 , G06F9/3824 , G06F9/3834 , G06F9/3851
摘要： A technique for scheduling execution of threads at a processor is disclosed. The technique includes executing a thread de-emphasis instruction of a thread that de-emphasizes the thread until the number of pending memory transactions, such as cache misses, associated with the thread are at or below a threshold. While the thread is de-emphasized, other threads at the processor that have a higher priority can be executed or assigned system resources. Accordingly, the likelihood of a stall in the processor is reduced.
摘要翻译： 公开了一种用于在处理器处调度线程执行的技术。 该技术包括执行线程的线程去加重指令，该线程去加强线程，直到与线程相关联的等待存储器事务（例如高速缓存未命中）的数量处于或低于阈值。 当该线程被去加强时，处理器中具有较高优先级的其他线程可以执行或分配系统资源。 因此，处理器中失速的可能性降低。
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15.发明授权Debug instruction for execution by a first thread to generate a debug event in a second thread to cause a halting operation 有权调试指令由第一个线程执行以在第二个线程中生成调试事件以导致暂停操作公开(公告)号：US09395983B2
公开(公告)日：2016-07-19
申请号：US12195220
申请日：2008-08-20
CPC分类号： G06F9/3005 , G06F9/3009 , G06F11/3648
摘要： For use in a data processing system comprising a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method is provided. The method comprises in response to execution of a debug related instruction by the first thread while executing the first set of instructions, generating a debug event for processing by the second thread, wherein processing the debug event comprises causing a halting operation related to the processor.
摘要翻译： 为了在包括处理器的数据处理系统中使用，该处理器被配置为执行对应于第一线程的第一组指令和对应于第二线程的第二组指令，提供了一种方法。 该方法包括响应于在执行第一组指令时由第一线程执行与调试相关的指令，生成用于由第二线程处理的调试事件，其中处理调试事件包括引起与处理器相关的暂停操作。
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公开(公告)号：US08531899B2
公开(公告)日：2013-09-10
申请号：US13613630
申请日：2012-09-13
IPC分类号： G11C7/00
CPC分类号： G11C29/24 , G11C5/147 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/83
摘要： A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array.
摘要翻译： 存储器系统具有包括冗余列的存储器单元阵列的第一存储器。 冗余列代替数组中的第一列。 第一列包括测试存储单元。 阵列接收电源电压。 测试存储单元在比阵列的存储单元更高的电源电压下变得不起作用。 存储器控制器耦合到第一存储器，并且用于确定测试存储器单元是否以电源电压的第一值起作用。 这对于对应用于阵列的电源电压的值做出决定是有用的。
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17.发明授权Integrated circuit having an embedded memory and method for testing the memory 有权具有嵌入式存储器的集成电路和用于测试存储器的方法公开(公告)号：US08379466B2
公开(公告)日：2013-02-19
申请号：US12414758
申请日：2009-03-31
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G11C5/147 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/83
摘要： A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array.
摘要翻译： 存储器系统具有包括冗余列的存储器单元阵列的第一存储器。 冗余列替代数组中的第一列。 第一列包括测试存储单元。 阵列接收电源电压。 测试存储单元在比阵列的存储单元更高的电源电压下变得不起作用。 存储器控制器耦合到第一存储器，并且用于确定测试存储器单元是否以电源电压的第一值起作用。 这对于对应用于阵列的电源电压的值做出决定是有用的。
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公开(公告)号：US08199547B2
公开(公告)日：2012-06-12
申请号：US12703528
申请日：2010-02-10
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G06F11/1064 , G11C29/52
摘要： A content addressable memory and method of operation uses a memory array having a plurality of rows of stored content addressable memory data and compare circuitry for comparing received comparand data with the stored content addressable memory data. A hit signal and one or more parity bits is provided for each row. Erroneous hit detection circuitry coupled to the memory array for each row generates a row error indicator in response to a comparison between parity of the comparand data and parity of a row that is correlated to the hit signal as qualified by assertion of a hit signal of that row. The erroneous hit detection circuitry uses the row error indicator for each row to provide an output which indicates whether at least one asserted hit signal corresponds to an erroneous hit.
摘要翻译： 内容可寻址存储器和操作方法使用具有多行存储的内容可寻址存储器数据的存储器阵列和用于将接收到的比较数据与存储的内容可寻址存储器数据进行比较的比较电路。 为每行提供命中信号和一个或多个奇偶校验位。 耦合到每行的存储器阵列的错误的命中检测电路响应于比较数据的奇偶性与与命中信号相关联的行的奇偶校验之间的比较，产生行错误指示，如通过断言该命中信号的命中信号 行。 错误的命中检测电路使用每一行的行错误指示符来提供指示至少一个被断言的命中信号是否对应于错误命中的输出。
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公开(公告)号：US20090172361A1
公开(公告)日：2009-07-02
申请号：US11967430
申请日：2007-12-31
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3861 , G06F9/3867
摘要： A thread switch mechanism and technique for a microprocessor is disclosed wherein a processing of a first thread is completed, and a continuation of a second thread is initiated during completion of the first thread. In one form, the technique includes processing a first thread at a pipeline of a processing device, and initiating processing of a second thread at a front end of the pipeline in response to an occurrence of a context switch event. The technique can also include initiating a instruction progress metric in response the context switch event. The technique can further include enabling completion of processing of instructions of the first thread that are at a back end of the pipeline at the occurrence of the context switch event until an expiry of the instruction progress metric.
摘要翻译： 公开了一种用于微处理器的线程切换机制和技术，其中完成了第一线程的处理，并且在完成第一线程期间开始了第二线程的延续。 在一种形式中，该技术包括处理处理设备的流水线处的第一线程，以及响应于上下文切换事件的发生，在流水线的前端开始处理第二线程。 该技术还可以包括响应于上下文切换事件发起指令进展度量。 该技术还可以包括在上下文切换事件发生时能够完成在流水线的后端处理第一线程的指令，直到指令进度度量的到期为止。
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20.发明申请INTEGRATED CIRCUIT MEMORY HAVING DYNAMICALLY ADJUSTABLE READ MARGIN AND METHOD THEREFOR 有权具有动态可调整性的集成电路存储器及其方法公开(公告)号：US20090103379A1
公开(公告)日：2009-04-23
申请号：US11875997
申请日：2007-10-22
申请人： Shayan Zhang , Hema Ramamurthy , Zheng Xu , Michael D. Snyder
发明人： Shayan Zhang , Hema Ramamurthy , Zheng Xu , Michael D. Snyder
CPC分类号： G11C29/02 , G11C11/41 , G11C29/026 , G11C29/028 , G11C2029/0409
摘要： A method for dynamically controlling sense amplifier differential margin of a memory during operation, in an integrated circuit, comprising a plurality of addressable units, is provided. The method includes setting the sense amplifier differential margin corresponding to the plurality of addressable units to a first value. The method further includes if a read data error occurs when data is read from a set of the plurality of addressable units, then setting the sense amplifier differential margin corresponding to the plurality of addressable units to a second value, wherein the second value is greater than the first value.
摘要翻译： 提供了一种用于在包括多个可寻址单元的集成电路中在操作期间动态地控制存储器的读出放大器差分裕度的方法。 该方法包括将与多个可寻址单元相对应的读出放大器差分裕度设置为第一值。 该方法还包括如果当从多个可寻址单元的集合读取数据时发生读取数据错误，则将与多个可寻址单元相对应的读出放大器差分裕度设置为第二值，其中第二值大于 第一个值。
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