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    Dual-control ring voltage controlled oscillator
    11.
    发明授权
    Dual-control ring voltage controlled oscillator 失效
    双控环压控振荡器

    公开(公告)号：US06396358B1

    公开(公告)日：2002-05-28

    申请号：US09773338

    申请日：2001-01-31

    Applicant: Joey Martin Poss ,  Scott Kevin Reynolds

    Inventor： Joey Martin Poss ,  Scott Kevin Reynolds

    IPC: H03B524

    CPC classification number: H03L7/0998 ,  H03K3/0315 ,  H03K5/133 ,  H03K2005/00071

    Abstract: A circuit of a dual control voltage-controlled ring oscillator is disclosed having significantly less power and area while still maintaining a large frequency range and tune accuracy. The dual control ring oscillator has at least two delay paths which can be added or interpolated according to an interpolation variable set by a coarse tune and a fine tune code. In addition, moreover, each of the delay paths have a number of variable delay elements which are varied in response to another input code. When the variable delay elements are capacitors, the capacitance will be varied in accordance with another coarse tune code. In the preferred embodiment, the input codes are digital and the frequency range obtained can be greater than two to one. First, the variable delay elements are adjusted to obtain coarse tuning of the dual control ring oscillator then the interpolation variable is more finely adjusted to obtain fine tuning of the ring oscillator. Phase control can be similarly accomplished using coarse tuning by adjusting the delay of the paths, and then using fine tuning to interpolate the delay paths.

    Abstract translation: 公开了一种双重控制压控环形振荡器的电路，其功率和面积显着降低，同时仍保持较大的频率范围和调谐精度。 双控制环形振荡器具有至少两个延迟路径，其可以根据由粗调和微调码设置的插值变量来相加或内插。 此外，每个延迟路径具有响应于另一个输入代码而变化的多个可变延迟元件。 当可变延迟元件是电容器时，电容将根据另一个粗调代码而变化。 在优选实施例中，输入代码是数字的，所获得的频率范围可以大于2比1。 首先，调整可变延迟元件以获得双重控制环形振荡器的粗调，然后更精细地调整内插变量以获得环形振荡器的微调。 可以通过调整路径的延迟，然后使用微调来内插延迟路径，使用粗调调类似地完成相位控制。

    Millimeter-wave switches and attenuators
    14.
    发明授权
    Millimeter-wave switches and attenuators 有权
    毫米波开关和衰减器

    公开(公告)号：US08279019B2

    公开(公告)日：2012-10-02

    申请号：US12776444

    申请日：2010-05-10

    Applicant: Sean Timothy Nicolson ,  Scott Kevin Reynolds

    Inventor： Sean Timothy Nicolson ,  Scott Kevin Reynolds

    IPC: H01P1/22

    CPC classification number: H03H7/25 ,  H01P1/15 ,  H04B1/40

    Abstract: An input attenuator may include a first input circuit having an RF_IN+ terminal, a first node, a transmission line, a DC blocking capacitor, a second node, a third node, and an output terminal coupled in series, the first node selectively coupled to ground via a serially coupled capacitor and a first silicon germanium heterojunction bipolar transistor, the second node coupled to ground via a capacitor, and the third node selectively coupled to ground via a DC blocking capacitor, a resistor, and a second silicon germanium heterojunction bipolar transistor coupled in series. The input attenuator may also include a second input circuit parallel to the first input circuit and having structure similar to the first input circuit.

    Abstract translation: 输入衰减器可以包括具有RF_IN +端子，第一节点，传输线，隔直流电容器，第二节点，第三节点和串联耦合的输出端的第一输入电路，第一节点选择性地耦合到地 经由串联耦合电容器和第一硅锗异质结双极晶体管，第二节点通过电容器耦合到地，并且第三节点经由隔直流电容器，电阻器和第二硅锗异质结双极晶体管选择性地耦合到地， 系列。 输入衰减器还可以包括与第一输入电路并联并具有与第一输入电路类似的结构的第二输入电路。

    QUADRATURE MODULATION CIRCUITS AND SYSTEMS SUPPORTING MULTIPLE MODULATION MODES AT GIGABIT DATA RATES
    15.
    发明申请
    QUADRATURE MODULATION CIRCUITS AND SYSTEMS SUPPORTING MULTIPLE MODULATION MODES AT GIGABIT DATA RATES 有权
    支持数字数据速率的多种调制模式的调制电路和系统

    公开(公告)号：US20100102895A1

    公开(公告)日：2010-04-29

    申请号：US11486539

    申请日：2006-07-14

    Applicant: Troy James Beukema ,  Alberto Valdes Garcia ,  Scott Kevin Reynolds

    Inventor： Troy James Beukema ,  Alberto Valdes Garcia ,  Scott Kevin Reynolds

    IPC: H04L27/20

    CPC classification number: H04L27/0008 ,  H04L27/04 ,  H04L27/2014 ,  H04L27/2057 ,  H04L27/206 ,  H04L27/362

    Abstract: Quadrature modulation systems, circuits and methods are provided to support various modulation modes including ASK (amplitude shift key), FSK (frequency shift key) and PSK (phase shift key) modulation at high data rates (e.g., gigabit data rates). For example, a modulation circuit includes a mixer circuit including an integrated sign modulation control circuit and a plurality of mixer ports. The mixer ports include a first input port, a second input port, an output port and a sign modulation control port. The modulation circuit generates a modulated signal by operation of the mixer circuit multiplying a modulating signal applied to the first input port with a carrier signal applied to the second input port to generate a mixed signal output from the output port, and by operation of the integrated sign modulation control circuit controlling polarity switching of a signal at one of the mixer ports in response to a sign modulation control signal input to the sign modulation control port. The sign modulation control signal can be a digital data signal having binary data encoded into the modulated signal.

    Abstract translation: 提供正交调制系统，电路和方法以支持在高数据速率（例如，千兆比特数据速率）下的ASK（振幅移位键），FSK（频移键）和PSK（相移键）调制的各种调制模式。 例如，调制电路包括具有集成符号调制控制电路和多个混频器端口的混频电路。 混频器端口包括第一输入端口，第二输入端口，输出端口和符号调制控制端口。 调制电路通过使施加到第一输入端口的调制信号与施加到第二输入端口的载波信号相乘的混频器电路的操作产生调制信号，以产生从输出端口输出的混合信号，并且通过集成 符号调制控制电路，响应于输入到符号调制控制端口的符号调制控制信号，控制混频器端口之一处的信号的极性切换。 符号调制控制信号可以是具有被编码为调制信号的二进制数据的数字数据信号。

    Integrated spectrum analyzer circuits and methods for providing on-chip diagnostics
    16.
    发明授权
    Integrated spectrum analyzer circuits and methods for providing on-chip diagnostics 有权
    用于提供片上诊断功能的集成频谱分析仪电路和方法

    公开(公告)号：US07688058B2

    公开(公告)日：2010-03-30

    申请号：US12212247

    申请日：2008-09-17

    Applicant: Keith Aelwyn Jenkins ,  Anup Paul Jose ,  Scott Kevin Reynolds

    Inventor： Keith Aelwyn Jenkins ,  Anup Paul Jose ,  Scott Kevin Reynolds

    IPC: G01R23/00 ,  G01R23/14

    CPC classification number: G01R23/16 ,  G01R23/20 ,  G01R31/316 ,  G01R31/3167

    Abstract: Spectrum analyzer circuits and methods are provided which implement “zero-IF” (direct conversion) or “near-zero IF” (or very low IF) architectures that enable implementation of integrated (on-chip) spectrum analyzers for measuring the frequency spectrum of internal chip signals. An integrated spectrum analyzer circuit, which comprises a zero IF or near-zero IF framework, enables a low-power compact design with sufficient resolution bandwidth for on-chip implementation and diagnostics of internal chip signals.

    Abstract translation: 提供了实现“零中频”（直接转换）或“近零中频”（或非常低的IF）架构的频谱分析仪电路和方法，其能够实现集成（片上）频谱分析仪，用于测量频谱 内部芯片信号。 包含零中频或近零IF框架的集成频谱分析仪电路实现了低功耗紧凑设计，具有足够的分辨率带宽，用于片内实现和内部芯片信号的诊断。

    Variable-Gain Image-Reject Low-Noise Amplifier
    17.
    发明申请
    Variable-Gain Image-Reject Low-Noise Amplifier 有权
    可变增益图像抑制低噪声放大器

    公开(公告)号：US20090015335A1

    公开(公告)日：2009-01-15

    申请号：US12127379

    申请日：2008-05-27

    Applicant: Brian Allan Floyd ,  Scott Kevin Reynolds

    Inventor： Brian Allan Floyd ,  Scott Kevin Reynolds

    IPC: H03G3/00 ,  G06F17/50

    CPC classification number: H03F3/16 ,  G06F17/5063 ,  H03F3/72 ,  H03G1/0088

    Abstract: A variable-gain amplifier includes an intermediate node operative to receive an electric current from a current source. A common-emitter amplifier has a collector electrically connected to the intermediate node. A first common-base amplifier has an emitter electrically connected to the intermediate node and a collector electrically connected to an output node. A base-degenerated amplifier has an emitter electrically connected to the intermediate node and a collector electrically connected to the output node. A second common-base amplifier has an emitter electrically connected to the intermediate node and a collector electrically connected to small-signal ground. The intermediate node is operative to direct the electric current to the first common-base amplifier, thereby causing the variable-gain amplifier to operate in a first mode; and the intermediate node is operative to direct the electric current to the base-degenerated amplifier and the second common-base amplifier, thereby causing the variable-gain amplifier to operate in a second mode.

    Abstract translation: 可变增益放大器包括可从电流源接收电流的中间节点。 共发射极放大器具有与中间节点电连接的集电极。 第一公共基极放大器具有电连接到中间节点的发​​射极和电连接到输出节点的集电极。 基极退化放大器具有电连接到中间节点的发​​射极和电连接到输出节点的集电极。 第二公共基极放大器具有电连接到中间节点的发​​射极和电连接到小信号地的集电极。 中间节点可操作地将电流引导到第一共基放大器，从而使可变增益放大器以第一模式工作; 并且中间节点可操作地将电流引导到基极退化的放大器和第二公共基极放大器，从而使可变增益放大器在第二模式下操作。

    Integrated millimeter-wave quadrature generator
    18.
    发明授权
    Integrated millimeter-wave quadrature generator 有权
    集成毫米波正交发生器

    公开(公告)号：US07386291B2

    公开(公告)日：2008-06-10

    申请号：US10653539

    申请日：2003-09-02

    Applicant: Brian Allan Floyd ,  Ullrich Richard Pfeiffer ,  Scott Kevin Reynolds ,  Thomas Martin Zwick

    Inventor： Brian Allan Floyd ,  Ullrich Richard Pfeiffer ,  Scott Kevin Reynolds ,  Thomas Martin Zwick

    IPC: H04B1/10

    CPC classification number: H04B1/30

    Abstract: An off-chip signal is provided to a differential branch-line directional coupler implemented entirely on-chip. The coupler produces differential quadrature signals, which are then buffered and applied to a quadrature mixer. The coupler is implemented entirely on-chip using microstrip transmission lines. The coupler is made up of a plurality of rings and a plurality of underpasses connecting ports of the rings, wherein each of the plurality of rings is made up of four branch lines, and each branch line having an electrical length of one-quarter wavelength at the center design frequency. Coupling between the plurality of branch lines of the rings may be varied.

    Abstract translation: 片外信号被提供给完全在芯片上实现的差分分支线定向耦合器。 耦合器产生差分正交信号，然后缓冲并施加到正交混频器。 耦合器使用微带传输线完全在片上实现。 耦合器由多个环和连接多个环的端口的多个地下通道组成，其中多个环中的每一个环由四个分支线构成，并且每个分支线具有四分之一波长的电长度 中心设计频率。 可以改变环的多个分支线之间的耦合。

    Circuits with dynamically biased active loads
    19.
    发明授权
    Circuits with dynamically biased active loads 失效
    具有动态偏置有功负载的电路

    公开(公告)号：US5909127A

    公开(公告)日：1999-06-01

    申请号：US601628

    申请日：1996-02-14

    Applicant: Dale Jonathan Pearson ,  Scott Kevin Reynolds

    Inventor： Dale Jonathan Pearson ,  Scott Kevin Reynolds

    IPC: H03K19/013 ,  H03K19/017 ,  H03K19/086 ,  H03K19/094 ,  H03K19/173

    CPC classification number: H03K19/01721 ,  H03K19/0136 ,  H03K19/086 ,  H03K19/09432 ,  H03K19/1738

    Abstract: This invention provides a circuit and method to replace the passive resistive or statically biased active load devices with dynamically biased active load devices. This allows the load devices to present an effective load which varies depending on the state of the circuit output. The effective load and the time rate of change of the effective load can be dynamically optimized to improve circuit performance with changing conditions. The effective load is varied according to the state of the circuit by the use of time-delayed negative feedback. The biasing of the load devices is also capable to control the logic swing of the circuit. A bias generating circuit employing a dynamically biased active load is described. This provides a method for a family of logic circuits, especially CML circuits, to operate at low voltage and low power at high switching speeds, having symmetrical rise and fall times and well defined logic signal swings. The output is sampled and maintained at near ideal bias voltage with a voltage follower type circuit which provides a gain of less than unity and finite delay. Particular circuit implementations using various semiconductor technologies are described and many others are possible. Although the invention may find primary use in VLSI logic circuits, especially those requiring high speed and low power, it is also shown to be useful in analog circuits. Alternate circuit configurations for dynamically biased active load devices are described.

    Abstract translation: 本发明提供一种用动态偏置的有源负载装置代替被动电阻或静态偏置有源负载装置的电路和方法。 这允许负载装置呈现根据电路输出的状态而变化的有效负载。 可以动态优化有效负载和有效负载的时间变化率，以改善电路性能。 根据电路的状态通过使用时间延迟的负反馈来改变有效负载。 负载装置的偏置也能够控制电路的逻辑摆幅。 描述了采用动态偏置的有源负载的偏置发生电路。 这提供了一种用于一系列逻辑电路，特别是CML电路的方法，其以高开关速度在低电压和低功率下工作，具有对称的上升和下降时间以及良好定义的逻辑信号摆幅。 输出采用电压跟随器电路采样并保持在接近理想的偏置电压，该电路提供小于一个和有限延迟的增益。 描述使用各种半导体技术的特定电路实现方式，并且许多其他实施方式是可能的。 尽管本发明可能在VLSI逻辑电路中发现主要用途，特别是那些需要高速度和低功率的逻辑电路，但是它也被证明在模拟电路中是有用的。 描述了用于动态偏置的有源负载装置的备用电路配置。

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