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11.发明授权公开(公告)号：US10388368B2
公开(公告)日：2019-08-20
申请号：US15799497
申请日：2017-10-31
Applicant: Seagate Technology LLC
Inventor： Ludovic Danjean , Sundararajan Sankaranarayanan , Erich F. Haratsch
Abstract: Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device for use with multi-level memory cells, comprises a controller configured to: after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of one or more of the multi-level memory cells has settled, determine a plurality of read reference voltages for the multi-level memory cells using a post-programming adaptive tracking algorithm; and employ the plurality of read reference voltages to read data from the multi-level memory cells. The reference voltage offsets are optionally determined based on a shift in the read reference voltages after the predefined time interval since the programming of the multi-level memory cells.
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12.发明申请公开(公告)号：US20190130966A1
公开(公告)日：2019-05-02
申请号：US15799484
申请日：2017-10-31
Applicant: Seagate Technology LLC
Inventor： Ludovic Danjean , Sundararajan Sankaranarayanan , Erich F. Haratsch
Abstract: Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device comprises a controller configured to: determine at least one reference voltage offset for a plurality of read reference voltages, wherein the at least one reference voltage offset is determined based on a shift in one or more of the read reference voltages over time; shift the plurality of read reference voltages using the at least one reference voltage offset; and employ the plurality of read reference voltages shifted by the at least one reference voltage offset to read data from the multi-level memory cells. The shifting step is optionally performed after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of the multi-level memory cells has settled. The reference voltage offsets are optionally determined based on a shift in the read reference voltages after a predefined time interval since a programming of the multi-level memory cells.
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公开(公告)号：US09633740B1
公开(公告)日：2017-04-25
申请号：US15041501
申请日：2016-02-11
Applicant: Seagate Technology LLC
Inventor： AbdelHakim S. Alhussien , Sundararajan Sankaranarayanan , Thuy Van Nguyen , Ludovic Danjean , Erich F. Haratsch
CPC classification number: G11C16/26 , G11C7/1006 , G11C11/5642 , G11C16/16 , G11C16/28 , G11C16/3418 , G11C16/3431 , H03M13/1111 , H03M13/1125 , H03M13/3746 , H03M13/6325
Abstract: Read retry operations in a memory employ likelihood value assignments that change sign at different read voltages for a plurality of read retry operations. A method for multiple read retries of a memory comprises reading a codeword using a first read voltage to obtain a first read value; mapping the first read value to first likelihood values based on a first likelihood value assignment that changes sign substantially at the first read voltage; reading the codeword using a second read voltage to obtain a second read value, wherein the second read voltage is shifted from the first read voltage to compensate for an expected change in analog voltages; and mapping the second read value to second likelihood values based on a second likelihood value assignment, wherein the second likelihood value assignment changes sign substantially at the second read voltage. Read data is optionally generated using iterative decoding of the codeword based on the first likelihood values and/or the second likelihood values.
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公开(公告)号：US11443826B2
公开(公告)日：2022-09-13
申请号：US16883081
申请日：2020-05-26
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Ludovic Danjean , Abdelhakim Alhussien , Erich Franz Haratsch
Abstract: Systems and methods presented herein provide for testing degradation in a storage device. In one embodiment, a storage controller is operable to test individual portions of a first of the plurality of storage areas of the storage device by: analyzing individual portions of the first storage area; determining that one or more of the individual portions of the first storage area have failed; and retire the failed one or more portions of the first storage area. The storage controller is further operable to write to the first storage area using an error correction code (ECC), and to test the remaining portions of the first storage area to determine whether the first storage area should be retired in response to writing to the first storage area.
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公开(公告)号：US10942655B2
公开(公告)日：2021-03-09
申请号：US16505909
申请日：2019-07-09
Applicant: Seagate Technology LLC
Inventor： Ludovic Danjean , Abdelhakim Alhussien , Sundararajan Sankaranarayanan , Erich Franz Haratsch
IPC: G06F3/06
Abstract: Systems and methods presented herein provide for mitigating errors in a storage device. In one embodiment, a storage system includes a storage device comprising a plurality of storage areas operable to store data, and a controller operable to evaluate operating conditions of the storage device, to perform a background scan on a first of the storage areas to characterize a read retention of the first storage area, and to adjust a read signal of the first storage area based on the characterized read retention and the operating conditions of the storage device.
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Patent Agency Ranking
公开(公告)号：US10699797B2
公开(公告)日：2020-06-30
申请号：US15964691
申请日：2018-04-27
Applicant: Seagate Technology LLC
Inventor： Ludovic Danjean , Abdelhakim Alhussien , Erich Franz Haratsch
Abstract: Systems and methods presented herein provide for testing degradation in a storage device. In one embodiment, a storage controller is operable to test individual portions of a first of the plurality of storage areas of the storage device by: analyzing individual portions of the first storage area; determining that one or more of the individual portions of the first storage area have failed; and retire the failed one or more portions of the first storage area. The storage controller is further operable to write to the first storage area using an error correction code (ECC), and to test the remaining portions of the first storage area to determine whether the first storage area should be retired in response to writing to the first storage area.
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公开(公告)号：US10666295B1
公开(公告)日：2020-05-26
申请号：US16225272
申请日：2018-12-19
Applicant: Seagate Technology LLC
Inventor： Ludovic Danjean , Sundararajan Sankaranarayanan , Ivana Djurdjevic , AbdelHakim Alhussien , Erich F. Haratsch
Abstract: An apparatus includes an interface and a control circuit. The interface may be configured to process transfers to/from a medium. The control circuit may be configured to generate a trapping set list of trapping sets of a low-density parity check code, classify bit positions of the trapping sets as belonging to either a user bits field or a parity bits field of a codeword, encode data using the low-density parity check code to generate the codeword, and present the codeword to the interface to transfer the codeword to the medium. The generation of the codeword may include at least one of a shortening or a puncturing of bit locations in the codeword in response to the classifying of the bit positions of the trapping sets. All of the data may be held in the bit locations of the codeword other than the bit locations that are shortened or punctured.
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公开(公告)号：US20190333599A1
公开(公告)日：2019-10-31
申请号：US15964691
申请日：2018-04-27
Applicant: Seagate Technology LLC
Inventor： Ludovic Danjean , Abdelhakim Alhussien , Erich Franz Haratsch
Abstract: Systems and methods presented herein provide for testing degradation in a storage device. In one embodiment, a storage controller is operable to test individual portions of a first of the plurality of storage areas of the storage device by: analyzing individual portions of the first storage area; determining that one or more of the individual portions of the first storage area have failed; and retire the failed one or more portions of the first storage area. The storage controller is further operable to write to the first storage area using an error correction code (ECC), and to test the remaining portions of the first storage area to determine whether the first storage area should be retired in response to writing to the first storage area.
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19.发明申请公开(公告)号：US20190130967A1
公开(公告)日：2019-05-02
申请号：US15799497
申请日：2017-10-31
Applicant: Seagate Technology LLC
Inventor： Ludovic Danjean , Sundararajan Sankaranarayanan , Erich F. Haratsch
CPC classification number: G11C11/5642 , G11C7/04 , G11C11/5635 , G11C16/22 , G11C16/26 , G11C16/349 , G11C2211/5644
Abstract: Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device for use with multi-level memory cells, comprises a controller configured to: after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of one or more of the multi-level memory cells has settled, determine a plurality of read reference voltages for the multi-level memory cells using a post-programming adaptive tracking algorithm; and employ the plurality of read reference voltages to read data from the multi-level memory cells. The reference voltage offsets are optionally determined based on a shift in the read reference voltages after the predefined time interval since the programming of the multi-level memory cells.
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公开(公告)号：US10263640B2
公开(公告)日：2019-04-16
申请号：US15478895
申请日：2017-04-04
Applicant: Seagate Technology LLC
Inventor： Ivana Djurdjevic , Ara Patapoutian , Zheng Wang , AbdelHakim Alhussien , Sundararajan Sankaranarayanan , Ludovic Danjean , Erich F. Haratsch
IPC: H03M13/11
Abstract: Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.
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