公开(公告)号：US07187617B2

公开(公告)日：2007-03-06

申请号：US11351836

申请日：2006-02-10

Applicant: Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

Inventor： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC: G11C8/00

CPC classification number: G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

Abstract: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

公开(公告)号：US20050134337A1

公开(公告)日：2005-06-23

申请号：US10744206

申请日：2003-12-22

Applicant: Seong-hoon Lee ,  Feng Lin

Inventor： Seong-hoon Lee ,  Feng Lin

IPC: G06F1/10 ,  H03L7/06 ,  H03L7/07 ,  H03L7/081 ,  H03L7/099

CPC classification number: H03L7/07 ,  G06F1/10 ,  H03L7/0812 ,  H03L7/0995

Abstract: Clock signal distribution systems with reduced parasitic loading effects are provided. A reference clock is frequency-divided to produce a lower frequency clock signal. A delay-locked loop (DLL) circuit locks to the lower frequency clock signal, and outputs a corresponding lower frequency clock signal for distribution over a long trace. Power consumption caused by parasitic capacitance of the trace is thereby reduced. Parasitic effects associated with clock jitter are also reduced. A frequency multiplying phase-locked loop (PLL) circuit locks to the lower frequency clock signal, and outputs at least one clock signal having a higher frequency than the lower frequency signal.

Abstract translation: 提供具有减小的寄生负载效应的时钟信号分配系统。 参考时钟被分频以产生较低频率的时钟信号。 延迟锁定环（DLL）电路锁定到较低频率时钟信号，并输出相应的较低频率时钟信号，以在较长的轨迹上分布。 因此，由于迹线的寄生电容引起的功耗降低。 与时钟抖动相关的寄生效应也降低。 频率倍增锁相环（PLL）电路锁定到较低频率时钟信号，并且输出具有比低频信号更高频率的至少一个时钟信号。

公开(公告)号：US07269094B2

公开(公告)日：2007-09-11

申请号：US11352131

申请日：2006-02-10

Applicant: Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

Inventor： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC: G11C8/00

CPC classification number: G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

Abstract: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

公开(公告)号：US20060126406A1

公开(公告)日：2006-06-15

申请号：US11352142

申请日：2006-02-10

Applicant: Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

Inventor： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC: G11C7/00

CPC classification number: G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

Abstract: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

公开(公告)号：US20080303570A1

公开(公告)日：2008-12-11

申请号：US11759782

申请日：2007-06-07

Applicant: Seong-hoon Lee

Inventor： Seong-hoon Lee

IPC: H03L7/00

CPC classification number: H03L7/07 ,  G06F1/10 ,  H03L7/0814

Abstract: Circuits, methods and systems are disclosed providing clock synchronization circuits for synchronized clock distribution for a plurality of devices in a semiconductor device. The clock synchronization apparatus includes an independent synchronization circuit and a dependent synchronization circuit. The independent synchronization circuit may provide synchronized clock distribution for a first destination while the dependent synchronization circuit may provide synchronized clock distribution to a second destination. A method for synchronized clock distribution to a plurality of destinations is also described.

Abstract translation: 公开了提供用于半导体器件中的多个器件的同步时钟分配的时钟同步电路的电路，方法和系统。 时钟同步装置包括独立同步电路和从属同步电路。 独立同步电路可以为第一目的地提供同步的时钟分配，而从属同步电路可以向第二目的地提供同步的时钟分配。 还描述了用于向多个目的地分配时钟的方法。

公开(公告)号：US07173463B2

公开(公告)日：2007-02-06

申请号：US11313291

申请日：2005-12-20

Applicant: Seong-hoon Lee

Inventor： Seong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03K5/15013 ,  H03K2005/00286 ,  H03L7/0818

Abstract: Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of serially-coupled HDs outputs clock signals that are phase-shifted relative to a reference clock signal. Each HD includes either one or two variable delay lines that provide coarse phase adjustment of an associated input signal. Each HD also includes one or more phase mixers that provide fine phase adjustment of the input signal.

公开(公告)号：US06952127B2

公开(公告)日：2005-10-04

申请号：US10719348

申请日：2003-11-21

Applicant: Seong-hoon Lee

Inventor： Seong-hoon Lee

IPC: G06F7/44 ,  G06G7/12 ,  H03K5/00 ,  H03K5/13 ,  H03K5/153

CPC classification number: H03K5/13 ,  H03K5/153 ,  H03K2005/00065

Abstract: Digital phase mixers with enhanced speed are provided. A phase mixer generates a signal having a phase between the phases of two input signals based on select signals. The propagation delay of the output signal is reduced by using a first voltage source to drive the input signals and the output signal and a second voltage source, having a higher voltage than the first voltage source, to drive the select signals. The higher voltage source reduces the impedance of each transistor driven by the select signals, thus reducing the propagation delay at the output of the phase mixer. For a non-differential digital phase mixer, the propagation delay is reduced in the rising edges of the output signal. For a differential digital phase mixer, the propagation delay is reduced in the rising and falling edges of the output signal.

公开(公告)号：US07423463B2

公开(公告)日：2008-09-09

申请号：US11489693

申请日：2006-07-18

Applicant: Adrian J Drexler ,  Debra M Bell ,  Tyler J Gomm ,  Seong-hoon Lee

Inventor： Adrian J Drexler ,  Debra M Bell ,  Tyler J Gomm ,  Seong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/08 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

公开(公告)号：US07161394B2

公开(公告)日：2007-01-09

申请号：US11204824

申请日：2005-08-16

Applicant: Seong-hoon Lee

Inventor： Seong-hoon Lee

IPC: H03B19/00

CPC classification number: H03K5/13 ,  H03K5/153 ,  H03K2005/00065

Abstract: Digital phase mixers with enhanced speed are provided. A phase mixer generates a signal having a phase between the phases of two input signals based on select signals. The propagation delay of the output signal is reduced by using a first voltage source to drive the input signals and the output signal and a second voltage source, having a higher voltage than the first voltage source, to drive the select signals. The higher voltage source reduces the impedance of each transistor driven by the select signals, thus reducing the propagation delay at the output of the phase mixer. For a non-differential digital phase mixer, the propagation delay is reduced in the rising edges of the output signal. For a differential digital phase mixer, the propagation delay is reduced in the rising and falling edges of the output signal.

Abstract translation: 提供了具有增强速度的数字相位混合器。 相位混合器基于选择信号产生具有两个输入信号的相位之间的相位的信号。 通过使用第一电压源来驱动输入信号和输出信号以及具有比第一电压源更高的电压的第二电压源来驱动输出信号的传播延迟来驱动选择信号。 较高的电压源降低了由选择信号驱动的每个晶体管的阻抗，从而降低了相位混合器输出端的传播延迟。 对于非差分数字相位混频器，输出信号的上升沿传播延迟减小。 对于差分数字相位混频器，输出信号的上升沿和下降沿传播延迟减小。

公开(公告)号：US20060038603A1

公开(公告)日：2006-02-23

申请号：US11204824

申请日：2005-08-16

Applicant: Seong-hoon Lee

Inventor： Seong-hoon Lee

IPC: G06G7/16

CPC classification number: H03K5/13 ,  H03K5/153 ,  H03K2005/00065

Abstract: Digital phase mixers with enhanced speed are provided. A phase mixer generates a signal having a phase between the phases of two input signals based on select signals. The propagation delay of the output signal is reduced by using a first voltage source to drive the input signals and the output signal and a second voltage source, having a higher voltage than the first voltage source, to drive the select signals. The higher voltage source reduces the impedance of each transistor driven by the select signals, thus reducing the propagation delay at the output of the phase mixer. For a non-differential digital phase mixer, the propagation delay is reduced in the rising edges of the output signal. For a differential digital phase mixer, the propagation delay is reduced in the rising and falling edges of the output signal.

Abstract translation: 提供了具有增强速度的数字相位混合器。 相位混合器基于选择信号产生具有两个输入信号的相位之间的相位的信号。 通过使用第一电压源来驱动输入信号和输出信号以及具有比第一电压源更高的电压的第二电压源来驱动输出信号的传播延迟来驱动选择信号。 较高的电压源降低了由选择信号驱动的每个晶体管的阻抗，从而降低了相位混合器输出端的传播延迟。 对于非差分数字相位混频器，输出信号的上升沿传播延迟减小。 对于差分数字相位混频器，输出信号的上升沿和下降沿传播延迟减小。