公开(公告)号：US20190131459A1

公开(公告)日：2019-05-02

申请号：US16091225

申请日：2017-04-07

Applicant: Sharp Kabushiki Kaisha

Inventor： Tadayoshi MIYAMOTO ,  Akihiro ODA

IPC: H01L29/786

Abstract: A gate driver TFT 30 includes: a gate electrode 30a; a channel portion 30d overlapping the gate electrode 30a with a gate insulating film 16 disposed therebetween and constructed from an oxide semiconductor film 17 that is a semiconductor film; a source electrode 30b connected to one end of the channel portion 30d; a drain electrode 30c connected to another end of the channel portion 30d; and an intermediate electrode 22 connected to the channel portion 30d at a position at which a distance L1 to the drain electrode 30c is greater than a distance L2 to the source electrode 30b.

公开(公告)号：US20170261790A1

公开(公告)日：2017-09-14

申请号：US15504963

申请日：2015-08-17

Applicant: Sharp Kabushiki Kaisha

Inventor： Yutaka TAKAMARU ,  Hiroshi MATSUKIZONO ,  Tadayoshi MIYAMOTO ,  TAKAO SAITOH ,  Yohsuke KANZAKI ,  Keisuke IDE

IPC: G02F1/1368 ,  G02F1/1343

CPC classification number: G02F1/1368 ,  G02F1/134363 ,  G02F1/136227 ,  G02F2001/134372 ,  G02F2201/121 ,  G02F2201/123 ,  G02F2201/40 ,  G02F2202/10 ,  H01L29/786

Abstract: A semiconductor device includes: a first substrate; a gate electrode on the first substrate; a gate insulating layer on the gate electrode; an oxide semiconductor film including a channel region disposed over the gate electrode through the gate insulating layer and lowered-resistance region contacting the channel region; a source electrode and a drain electrode on the channel region; a first insulating film covering at least the channel region and including a contact hole that exposes the lowered-resistance region; and a second insulating film having reducing characteristics and disposed above the first insulating film across the contact hole, the second insulating film contacting the lowered-resistance region inside the contact hole.

公开(公告)号：US20170236856A1

公开(公告)日：2017-08-17

申请号：US15501506

申请日：2015-07-30

Applicant: Sharp Kabushiki Kaisha

Inventor： Kazuhide TOMIYASU ,  Tadayoshi MIYAMOTO

IPC: H01L27/146 ,  H04N5/32 ,  G01T1/20

CPC classification number: H01L27/14603 ,  G01T1/2018 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/1225 ,  H01L27/144 ,  H01L27/146 ,  H01L27/14616 ,  H01L27/14636 ,  H01L27/14663 ,  H01L27/14689 ,  H01L29/78693 ,  H04N5/32

Abstract: It is an object of the invention to secure a large area of a photodiode and suppress operation property variation and malfunction in an imaging panel and an X-ray imaging device. An imaging panel (10) includes a substrate (40), a TFT (14), an interlayer insulating film (44), a metal layer (45), and a photodiode (15). A data line (12) and the photodiode (15) face each other in a thickness direction of the substrate. The interlayer insulating film (44), which is disposed between the TFT (14) and the photodiode (15), is an SOG film or a photosensitive resin film.

公开(公告)号：US20170125452A1

公开(公告)日：2017-05-04

申请号：US15318622

申请日：2015-06-09

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Keisuke IDE ,  Takao SAITOH ,  Yohsuke KANZAKI ,  Yutaka TAKAMARU ,  Seiji KANEKO ,  Hiroshi MATSUKIZONO ,  Tadayoshi MIYAMOTO

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  G09G3/36 ,  G02F1/1368

CPC classification number: H01L27/1251 ,  G02F1/13624 ,  G02F1/1368 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2330/021 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1274 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/78675 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device (100) includes a substrate (11), a first TFT (10), and a second TFT (20). The first TFT includes a first semiconductor layer (12) that is supported by the substrate, a first gate electrode (14) that is formed on the first semiconductor layer and overlaps with the first semiconductor layer with a first gate insulating layer (13) interposed therebetween, a first insulating layer (16) that covers the first gate electrode, and a first source electrode (17s) and a first drain electrode (17d) that are formed on the first insulating layer and are connected to the first semiconductor layer. The second TFT includes a second gate electrode (22) that is supported by the substrate, a second semiconductor layer (25) that contains an oxide semiconductor and is formed overlapping with the second gate electrode with a second gate insulating layer (23) interposed therebetween, and a second source electrode (24s) and a second drain electrode (24d) that are formed between the second gate insulating layer and the second semiconductor layer. The first semiconductor layer and the second gate electrode are both formed from a same semiconductor film (52).