公开(公告)号：US20100109148A1

公开(公告)日：2010-05-06

申请号：US12604385

申请日：2009-10-22

申请人： Kunihiro Yamashita ,  Kazushi Hatauchi ,  Naoki Izumi ,  Akira Yamazaki

发明人： Kunihiro Yamashita ,  Kazushi Hatauchi ,  Naoki Izumi ,  Akira Yamazaki

IPC分类号： H01L23/495 ,  H01L23/31

CPC分类号： H01L23/49503 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83855 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： When a second semiconductor chip is mounted onto a first semiconductor chip, collision of the first semiconductor chip with a lead frame is to be prevented. The lead frame has a die pad and suspending leads for supporting the die pad. A joining portion is provided over the lead frame. The first semiconductor chip is provided over the lead frame through the joining portion. The second semiconductor chip is provided over the first semiconductor chip. A resin member covers the die pad and the first and second semiconductor chips. The joining portion is positioned over each of the die pad and the suspending leads.

摘要翻译： 当将第二半导体芯片安装到第一半导体芯片上时，可以防止第一半导体芯片与引线框架的碰撞。 引线框架具有管芯焊盘和用于支撑管芯焊盘的悬挂引线。 接合部分设置在引线框架上。 第一半导体芯片通过接合部分设置在引线框架上。 第二半导体芯片设置在第一半导体芯片上。 树脂构件覆盖芯片焊盘和第一和第二半导体芯片。 接合部分位于每个管芯焊盘和悬挂引线上。

公开(公告)号：US09299833B2

公开(公告)日：2016-03-29

申请号：US12232011

申请日：2008-09-09

申请人： Naoki Izumi ,  Tomoyasu Sada

发明人： Naoki Izumi ,  Tomoyasu Sada

IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423

CPC分类号： H01L29/7824 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66681

摘要： A semiconductor device according to the present invention includes: an insulating layer; a semiconductor layer of a first conductive type laminated on the insulating layer; an annular deep trench having a thickness reaching the insulating layer from a top surface of the semiconductor layer; a body region of a second conductive type formed across an entire thickness of the semiconductor layer along a side surface of the deep trench in an element forming region surrounded by the deep trench; a drift region of the first conductive type constituted of a remainder region besides the body region in the element forming region; a source region of the first conductive type formed in a top layer portion of the body region; a drain region of the first conductive type formed in a top layer portion of the drift region; and a first conductive type region formed in the drift region, having a deepest portion reaching a position deeper than the drain region, and having a first conductive type impurity concentration higher than the first conductive type impurity concentration of the semiconductor layer and lower than the first conductive type impurity concentration of the drain region.

摘要翻译： 根据本发明的半导体器件包括：绝缘层; 层叠在绝缘层上的第一导电类型的半导体层; 环形深沟槽，其厚度从半导体层的顶表面到达绝缘层; 在由所述深沟槽包围的元件形成区域中沿着所述深沟槽的侧表面横跨所述半导体层的整个厚度形成的第二导电类型的主体区域; 所述第一导电类型的漂移区域由除了所述元件形成区域中的所述主体区域之外的余下区域构成; 所述第一导电类型的源极区域形成在所述主体区域的顶层部分中; 所述第一导电类型的漏区形成在所述漂移区的顶层部分中; 以及形成在所述漂移区域中的第一导电类型区域，其最深部分到达比所述漏极区域更深的位置，并且具有比所述半导体层的所述第一导电类型杂质浓度高的第一导电型杂质浓度，并且低于所述第一导电类型区域 漏区的导电型杂质浓度。

公开(公告)号：US08829679B2

公开(公告)日：2014-09-09

申请号：US13534844

申请日：2012-06-27

申请人： Hiroyuki Chibahara ,  Atsushi Ishii ,  Naoki Izumi ,  Masahiro Matsumoto

发明人： Hiroyuki Chibahara ,  Atsushi Ishii ,  Naoki Izumi ,  Masahiro Matsumoto

IPC分类号： H01L23/48

CPC分类号： H01L23/02 ,  H01L23/522 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.

摘要翻译： 提供了难以发生由层间电介质膜的破裂引起的密封环破坏的半导体装置，以及半导体装置的制造方法。 第一层压板包括具有第一机械强度的第一层间绝缘膜。 第二层压体包括具有高于第一机械强度的机械强度的第二层间介电膜。 第一区域包括设置在第一层压体内的第一金属层和通孔。 第二区域包括设置在第二层压体内的第二金属层和通孔。 当在平面图中看到时，第二区域与第一区域的至少一部分重叠，不通过通孔与第一区域耦合，并且在其与第一区域之间夹住第二层间电介质膜。

公开(公告)号：US08476702B2

公开(公告)日：2013-07-02

申请号：US12238556

申请日：2008-09-26

申请人： Naoki Izumi

发明人： Naoki Izumi

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L27/088 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/7813

摘要： A semiconductor device according to the present invention includes: a body region of a first conductive type; trenches formed by digging in from a top surface of the body region; gate electrodes embedded in the trenches; source regions of a second conductive type formed at sides of the trenches in a top layer portion of the body region; and body contact regions of the first conductive type, penetrating through the source regions in a thickness direction and contacting the body region. The body contact regions are formed in a zigzag alignment in a plan view. With respect to a column formed by the body contact regions aligned in a predetermined column direction, the trenches are disposed at both sides in a row direction orthogonal to the column direction in a plan view, extend in the column direction, and form meandering lines each connecting a plurality of curved portions so that a predetermined gap in the row direction is formed respectively between adjacent trenches extending in the column direction and between the trenches and the body contact regions.

摘要翻译： 根据本发明的半导体器件包括：第一导电类型的体区; 通过从身体区域的顶表面挖入而形成的沟槽; 嵌入沟槽中的栅电极; 源区域，形成在所述体区域的顶层部分中的所述沟槽的侧面处的第二导电类型; 以及第一导电类型的身体接触区域，其在厚度方向上穿过源区域并接触身体区域。 身体接触区域在平面图中以Z字形排列形成。 对于由预定列方向排列的身体接触区域形成的列，在平面图中沿着与列方向正交的行方向的两侧配置沟槽，在列方向上延伸，并且形成曲折线 连接多个弯曲部分，使得在列方向上延伸的相邻沟槽之间以及沟槽与身体接触区域之间分别形成在行方向上的预定间隙。

公开(公告)号：US08426912B2

公开(公告)日：2013-04-23

申请号：US12285012

申请日：2008-09-26

申请人： Naoki Izumi

发明人： Naoki Izumi

IPC分类号： H01L27/88 ,  H01L21/8234

CPC分类号： H01L29/0646 ,  H01L21/761 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/823487 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/4236 ,  H01L29/66719 ,  H01L29/66734

摘要： A semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type; a body region of a second conductivity type formed in a surface layer portion of the semiconductor layer; a trench dug from the surface of the semiconductor layer to penetrate the body region; a source region of a first conductivity type formed on a side portion of the trench in a surface layer portion of the body region; a gate insulating film formed on the bottom surface and the side surface of the trench; a gate electrode embedded in the trench through the gate insulating film and so formed that the surface thereof is lower by one stage than the surface of the source region; and a peripheral wall film formed on a peripheral edge portion of the surface of the gate electrode to be opposed to an upper end portion of the side surface of the trench.

公开(公告)号：US20120267793A1

公开(公告)日：2012-10-25

申请号：US13534844

申请日：2012-06-27

申请人： Hiroyuki Chibahara ,  Atsushi Ishii ,  Naoki Izumi ,  Masahiro Matsumoto

发明人： Hiroyuki Chibahara ,  Atsushi Ishii ,  Naoki Izumi ,  Masahiro Matsumoto

IPC分类号： H01L23/498

CPC分类号： H01L23/02 ,  H01L23/522 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.

摘要翻译： 提供了难以发生由层间电介质膜的破裂引起的密封环破坏的半导体装置，以及半导体装置的制造方法。 第一层压板包括具有第一机械强度的第一层间绝缘膜。 第二层压体包括具有高于第一机械强度的机械强度的第二层间介电膜。 第一区域包括设置在第一层压体内的第一金属层和通孔。 第二区域包括设置在第二层压体内的第二金属层和通孔。 当在平面图中看到时，第二区域与第一区域的至少一部分重叠，不通过通孔与第一区域耦合，并且在其与第一区域之间夹住第二层间电介质膜。

公开(公告)号：US08269312B2

公开(公告)日：2012-09-18

申请号：US12457172

申请日：2009-06-03

申请人： Naoki Izumi

发明人： Naoki Izumi

IPC分类号： H01L29/00

CPC分类号： H01L27/0629 ,  H01L21/26513 ,  H01L21/26586 ,  H01L28/20 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

摘要： A semiconductor device according to an aspect of the present invention includes a semiconductor layer, an insulating film formed on the surface of the semiconductor layer, a first insulator embedded in the semiconductor layer with a thickness larger than the thickness of the insulating film, and a resistive element formed on the first insulator. A semiconductor device according to another aspect of the present invention includes a semiconductor layer, an insulating film formed on the surface of the semiconductor layer, a resistive element formed on the insulating film, and a floating region formed on a portion of the semiconductor layer opposed to the resistive element through the insulating film and electrically floating from a periphery thereof.

摘要翻译： 根据本发明的一个方面的半导体器件包括半导体层，形成在半导体层的表面上的绝缘膜，嵌入到半导体层中的厚度大于绝缘膜的厚度的第一绝缘体，以及 电阻元件形成在第一绝缘体上。 根据本发明的另一方面的半导体器件包括半导体层，形成在半导体层的表面上的绝缘膜，形成在绝缘膜上的电阻元件和形成在半导体层相对的部分上的浮动区域 通过绝缘膜到电阻元件，并从其周边电浮动。

公开(公告)号：US08217443B2

公开(公告)日：2012-07-10

申请号：US12470439

申请日：2009-05-21

申请人： Naoki Izumi

发明人： Naoki Izumi

IPC分类号： H01L29/788

CPC分类号： H01L29/788 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42336 ,  H01L29/7881

摘要： A semiconductor device includes a semiconductor layer having a trench; a source region formed in a surface layer portion thereof adjacently to a first side of the trench; a drain region formed in the surface layer portion adjacently to a second side of the trench; a first insulating film formed in the trench; a floating gate stacked on the first insulating film and opposed to the trench, and extending over and covering only partially the source and drain regions; a second insulating film formed on the floating gate; and a control gate at least partially embedded in the trench so that a portion embedded in the trench is opposed to the floating gate through the second insulating film. The first insulating film has a thin portion in contact with the drain region and a thick portion formed by the remainder thereof which covers the entire bottom surface of the trench.

摘要翻译： 半导体器件包括具有沟槽的半导体层; 源极区，形成在与沟槽的第一侧相邻的表面层部分中; 漏极区，形成在所述表面层部分中相邻于所述沟槽的第二侧; 在沟槽中形成的第一绝缘膜; 堆叠在所述第一绝缘膜上并与所述沟槽相对的浮栅，并且仅在所述源极和漏极区域上部分延伸并覆盖; 形成在浮动栅极上的第二绝缘膜; 以及至少部分地嵌入所述沟槽中的控制栅极，使得嵌入所述沟槽中的部分通过所述第二绝缘膜与所述浮置栅极相对。 第一绝缘膜具有与漏区接触的薄部分和由覆盖沟槽的整个底表面的剩余部分形成的厚部分。

公开(公告)号：US08174066B2

公开(公告)日：2012-05-08

申请号：US12222461

申请日：2008-08-08

申请人： Naoki Izumi

发明人： Naoki Izumi

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66734

摘要： A semiconductor device includes: a semiconductor layer; a first conductivity type region of a first conductivity type formed in a base layer portion of the semiconductor layer; a body region of a second conductivity type formed in the semiconductor layer to be in contact with the first conductivity type region; a trench formed by digging the semiconductor layer from the surface thereof to pass through the body region so that the deepest portion thereof reaches the first conductivity type region; a gate insulating film formed on the bottom surface and the side surface of the trench; a gate electrode buried in the trench through the gate insulating film; a source region of the first conductivity type formed in a surface layer portion of the semiconductor layer on a side in a direction orthogonal to the gate width with respect to the trench to be in contact with the body region; and a high-concentration region of the second conductivity type, formed in the body region on a position opposed to the trench in the direction orthogonal to the gate width, having a higher second conductivity type impurity concentration than that of the periphery thereof.

摘要翻译： 半导体器件包括：半导体层; 形成在半导体层的基底层部分中的第一导电类型的第一导电类型区域; 在半导体层中形成的与第一导电类型区域接触的第二导电类型的体区; 通过从半导体层的表面挖掘半导体层而通过体区，使其最深部到达第一导电型区域而形成的沟槽; 形成在沟槽的底表面和侧表面上的栅极绝缘膜; 通过栅极绝缘膜掩埋在沟槽中的栅电极; 所述第一导电类型的源极区域形成在所述半导体层的表面层部分中，所述源极区域在与栅极宽度正交的方向上相对于所述沟槽与所述主体区域接触; 以及形成在与栅极宽度正交的方向上与沟槽相对的位置处的体区中具有比其周边高的第二导电型杂质浓度的高浓度区域。

公开(公告)号：US20110266657A1

公开(公告)日：2011-11-03

申请号：US13180202

申请日：2011-07-11

申请人： Hiroyuki Chibahara ,  Atsushi Ishii ,  Naoki Izumi ,  Masahiro Matsumoto

发明人： Hiroyuki Chibahara ,  Atsushi Ishii ,  Naoki Izumi ,  Masahiro Matsumoto

IPC分类号： H01L23/02

CPC分类号： H01L23/02 ,  H01L23/522 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.

摘要翻译： 提供了难以发生由层间电介质膜的破裂引起的密封环破坏的半导体装置，以及半导体装置的制造方法。 第一层压板包括具有第一机械强度的第一层间绝缘膜。 第二层压体包括具有高于第一机械强度的机械强度的第二层间介电膜。 第一区域包括设置在第一层压体内的第一金属层和通孔。 第二区域包括设置在第二层压体内的第二金属层和通孔。 当在平面图中看到时，第二区域与第一区域的至少一部分重叠，不通过通孔与第一区域耦合，并且在其与第一区域之间夹住第二层间电介质膜。