公开(公告)号：US06214680B1

公开(公告)日：2001-04-10

申请号：US09460111

申请日：1999-12-13

申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Puay Ink Ong ,  Sang Yee Loong

发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Puay Ink Ong ,  Sang Yee Loong

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545

摘要： A new method of fabricating a MOSFET device is described. A semiconductor substrate is provided and isolation areas are formed isolating active areas in the substrate. An oxide layer is provided overlying both the substrate and isolation area and is patterned and etched to expose two areas within an isolated active area of the substrate. Selective epitaxial growth (SEG) using intrinsic silicon is performed to fill the exposed substrate areas formed in the previous etch step. The oxide layer region in the active area between the two epitaxially grown silicon regions is then etched, exposing the substrate. This is followed by a gate oxide growth and a polysilicon deposition. Planarization is then performed on the surface to expose the two epitaxially grown silicon regions. A second oxide is grown consuming some of the polysilicon gate and the epitaxially grown silicon. This consumption occurs at a higher rate at the upper surface and thus shapes the gate and epitaxially grown silicon into trapezoids with the base being wider than the top. The oxide is then etched leaving V-shaped trenches between the polysilicon and epitaxially grown silicon. A low-angle implantation is performed creating the source/drain extensions in the substrate below the V-shaped trenches. A third oxide is deposited filling the V-shaped groove and overlying the surface of the wafer. A second planarization is performed exposing the top of the epitaxially grown silicon regions and the polysilicon gate. A second implantation is performed to dope the polysilicon gate and epitaxially grown silicon regions. The doped portions of the epitaxially grown silicon form the source drain electrodes of the MOSFET. This is then followed by a salicidation step for metalization and annealing of the second implantation completing the MOSFET device.

摘要翻译： 描述了一种制造MOSFET器件的新方法。 提供半导体衬底，并且形成隔离区域以隔离衬底中的有源区域。 提供覆盖衬底和隔离区域的氧化物层，并且被图案化和蚀刻以暴露衬底的隔离有效区域内的两个区域。 执行使用本征硅的选择性外延生长（SEG）以填充在先前蚀刻步骤中形成的暴露的衬底区域。 然后蚀刻两个外延生长的硅区域之间的有源区域中的氧化物层区域，暴露衬底。 之后是栅极氧化物生长和多晶硅沉积。 然后在表面上进行平面化以暴露两个外延生长的硅区域。 第二氧化物生长消耗一些多晶硅栅极和外延生长的硅。 这种消耗以较高的速率发生在上表面，因此将浇口和外延生长的硅形成为梯形，基部比顶部宽。 然后蚀刻氧化物，留下多晶硅和外延生长的硅之间的V形沟槽。 执行低角度注入，在V形沟槽下面的衬底中产生源极/漏极延伸部。 沉积填充V形槽并覆盖晶片表面的第三氧化物。 进行外延生长的硅区域和多晶硅栅极的顶部的第二平面化。 进行第二次注入以掺杂多晶硅栅极和外延生长的硅区域。 外延生长硅的掺杂部分形成MOSFET的源极漏极。 然后进行用于金属化和退火完成MOSFET器件的第二次注入的盐析步骤。

公开(公告)号：US06258677B1

公开(公告)日：2001-07-10

申请号：US09409875

申请日：1999-10-01

申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

IPC分类号： H01L21336

CPC分类号： H01L29/0847 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/76283 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66651

摘要： A method of fabricating a transistor, comprising the following steps. A silicon semiconductor structure having spaced, raised, wedge-shaped dielectric isolation regions defining an active region there between is provided. Epitaxial silicon is grown over the active area to form an SEG region. A dummy gate is formed over the SEG region. Raised epitaxial silicon layers are grown over the SEG region adjacent the dummy gate. The dummy gate is removed, exposing the interior side walls of the raised epitaxial silicon layers. Sidewall spacers are formed on the exposed sidewalls of the raised epitaxial silicon layers. A gate oxide layer is grown over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. A layer of polysilicon is deposited over the structure and is planarized to form a gate conductor over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. The sidewall spacers are removed. No HDP process trench fill is required to form the STIs and no CMP process is required to planarized the STIs.

摘要翻译： 一种制造晶体管的方法，包括以下步骤。 提供了具有限定其间的有源区域的具有间隔开的凸起的楔形介电隔离区域的硅半导体结构。 在活性区域上生长外延硅以形成SEG区域。 在SEG区域上形成一个虚拟门。 凸起的外延硅层生长在与虚拟栅极相邻的SEG区域上。 去除虚拟栅极，暴露凸起的外延硅层的内侧壁。 在凸起的外延硅层的暴露的侧壁上形成侧壁间隔物。 栅极氧化物层生长在SEG区域上并且在凸起的外延硅层的侧壁间隔物之间​​。 在该结构上沉积一层多晶硅，并将其平坦化，以在SEG区域和凸出的外延硅层的侧壁间隔物之间​​形成栅极导体。 去除侧壁间隔物。 不需要HDP工艺沟槽填充来形成STI，并且不需要CMP工艺来平坦化STI。

公开(公告)号：US06248618B1

公开(公告)日：2001-06-19

申请号：US09415246

申请日：1999-10-12

申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Puay Ing Ong ,  Sang Yee Loong

发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Puay Ing Ong ,  Sang Yee Loong

IPC分类号： H01L218238

CPC分类号： H01L21/823857 ,  Y10S438/981

摘要： A method of forming thick and thin gate oxides comprising the following steps. A silicon semiconductor substrate having first and second active areas separated by shallow isolation trench regions is provided. Oxide growth is selectively formed over the first active area by UV oxidation to form a first gate oxide layer having a first predetermined thickness. The first and second active areas are then simultaneously oxidized whereby the first predetermined thickness of the first gate oxide layer is increased to a second predetermined thickness and a second gate oxide layer having a predetermined thickness is formed in the second active area. The second predetermined thickness of the first oxide layer in the first active area is greater than the predetermined thickness of the second oxide layer in the second active area.

摘要翻译： 一种形成厚薄的栅极氧化物的方法，包括以下步骤。 提供具有由浅隔离沟槽区域隔开的第一和第二有源区的硅半导体衬底。 通过UV氧化在第一有源区上选择性地形成氧化物生长，以形成具有第一预定厚度的第一栅氧化层。 然后，第一和第二有源区域被同时氧化，由此第一栅极氧化物层的第一预定厚度增加到第二预定厚度，并且在第二有源区域中形成具有预定厚度的第二栅极氧化物层。 第一有源区中的第一氧化物层的第二预定厚度大于第二有源区中第二氧化物层的预定厚度。

公开(公告)号：US06963113B2

公开(公告)日：2005-11-08

申请号：US10915670

申请日：2004-08-10

申请人： Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

发明人： Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/66772 ,  H01L29/78615

摘要： A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. A second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.

摘要翻译： 描述了一种在消除浮体效应的同时形成绝缘体上硅MOSFET的新方法。 提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下面的硅半导体衬底。 第一沟槽部分地被蚀刻穿过硅层而不是蚀刻到下面的氧化物层。 第二沟槽被完全蚀刻通过硅层到下面的氧化物层，其中第二沟槽分离半导体衬底的有源区域，并且其中第一沟槽中的一个位于每个有源区域内。 第一和第二沟槽填充有绝缘层。 栅极电极和相关的源极和漏极区域形成在每个有源区域中的硅层中和硅层上。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 在每个有源区域中通过层间电介质层形成第二接触开口，其中第二接触开口接触第一沟槽和第二沟槽中的一个沟槽。 第一和第二接触开口填充有导电层，以在集成电路的制造中完成绝缘体上硅器件的形成。

公开(公告)号：US06582856B1

公开(公告)日：2003-06-24

申请号：US09513872

申请日：2000-02-28

申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Song ,  Sang Yee Loong

发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Song ,  Sang Yee Loong

IPC分类号： G03F900

CPC分类号： G03F1/29

摘要： A new method of fabricating a rim phase shifting mask is achieved. An opaque layer is provided overlying a transparent substrate. A resist layer is deposited overlying the opaque layer. The resist layer is patterned. The opaque layer and the transparent substrate are etched. The resist layer masks this etching. The opaque layer is etched through during this etching. Notches are thereby etched into the transparent substrate at the edges of the opaque layer. These notches will cause a phase shift in incident light relative to incident light passing through regions in the transparent substrate adjacent to the notches. During this etching, an overetch is performed to remove any mask defects in the transparent substrate. Optionally, the notches may be etched into a phase shifting layer overlying the transparent substrate. An etch stopping layer may also be used in the phase shifting layer embodiment.

摘要翻译： 实现了制作边缘相移掩模的新方法。 在透明基底上方设置不透明层。 将抗蚀剂层沉积在不透明层上。 抗蚀剂层被图案化。 蚀刻不透明层和透明基板。 抗蚀剂层掩盖该蚀刻。 在该蚀刻期间蚀刻不透明层。 因此，在不透明层的边缘处，凹口被蚀刻到透明基板中。 这些凹口将引起入射光相对于穿过透明衬底中与凹口相邻的区域的入射光的相移。 在该蚀刻期间，执行过蚀刻以去除透明基板中的任何掩模缺陷。 可选地，凹口可被蚀刻到覆盖透明衬底的相移层中。 在相移层实施例中也可以使用蚀刻停止层。

公开(公告)号：US06492726B1

公开(公告)日：2002-12-10

申请号：US09667837

申请日：2000-09-22

申请人： Shyue Fong Quek ,  Ying Keung Leung ,  Sang Yee Loong ,  Ting Cheong Ang

发明人： Shyue Fong Quek ,  Ying Keung Leung ,  Sang Yee Loong ,  Ting Cheong Ang

IPC分类号： H01L2348

CPC分类号： H01L23/36 ,  H01L23/055 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In accordance with the objectives of the invention a new package is provided that is provided with a cavity that is shaped such that more than one semiconductor device can in a vertical direction be mounted in the cavity of the package. The devices that are mounted inside the cavity of the package are separated by separate components of insulation, the overlying devices are electrically interconnected by horizontally positioned solder bumps and vertical interconnect plugs.

摘要翻译： 根据本发明的目的，提供了一种新的封装，其具有形成使得多于一个半导体器件可以在垂直方向上可以安装在封装的空腔中的空腔。 安装在封装腔内的器件由绝缘体的分开的部件隔开，上覆的器件通过水平定位的焊料凸块和垂直互连插头电互连。

公开(公告)号：US06406948B1

公开(公告)日：2002-06-18

申请号：US09615807

申请日：2000-07-13

申请人： Song Jun ,  Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek

发明人： Song Jun ,  Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek

IPC分类号： H01L2184

CPC分类号： H01L27/0251 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. An N-well is formed within a silicon semiconductor substrate. A P+ region is implanted within a portion of the N-well and an N+ region is implanted within a portion of the semiconductor substrate not occupied by the N-well. An oxide layer is formed overlying the semiconductor substrate and patterned to form openings to the semiconductor substrate. An epitaxial silicon layer is grown within the openings and overlying the oxide layer. Shallow trench isolation regions are formed within the epitaxial silicon layer extending to the underlying oxide layer. Gate electrodes and associated source and drain regions are formed in and on the epitaxial silicon layer between the shallow trench isolation regions. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. The interlevel dielectric layer is covered with a mask that covers the first contact openings. Second contact openings are opened through the interlevel dielectric layer, shallow trench isolations, and the oxide layer to the N+ region and P+ region. The mask is removed. The first and second contact openings are filled with a conducting layer to complete formation of an ESD device.

摘要翻译： 描述了使用绝缘体上硅技术形成静电放电装置的方法。 在硅半导体衬底内形成N阱。 将P +区注入到N阱的一部分内，并且将N +区注入到不被N阱占据的半导体衬底的一部分内。 在半导体衬底上形成氧化物层并图案化以形成到半导体衬底的开口。 外延硅层生长在开口内并覆盖氧化物层。 在延伸到下面的氧化物层的外延硅层内形成浅沟槽隔离区。 在浅沟槽隔离区域之间的外延硅层中和栅极电极和相关的源极和漏极区域上形成栅电极。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 用覆盖第一接触开口的掩模覆盖层间电介质层。 第二接触开口通过层间介质层，浅沟槽隔离层和氧化物层开放到N +区域和P +区域。 去除面具。 第一和第二接触开口填充有导电层以完成ESD装置的形成。

公开(公告)号：US06764914B2

公开(公告)日：2004-07-20

申请号：US10290130

申请日：2002-11-07

申请人： Alex See ,  Cher Liang Randall Cha ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

发明人： Alex See ,  Cher Liang Randall Cha ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L21/31683

摘要： A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures. A second iteration features the exposure of specific regions of an underlying metal layer, to a UV, or to an I line exposure procedure, performed in an oxidizing ambient, with the regions of an underlying metal layer exposed to the UV or I line procedure, via clear regions in an overlying photolithographic plate. This procedure also results in the formation of a high K layer, on a top portion of the underlying metal layer.

摘要翻译： 在高于周围结构所经历的温度的温度下进行的金属氧化物 - 金属电容器结构的高介电常数（高K）层，其特征在于底层金属层的局部氧化， 已经开发 该方法的第一次迭代的特征在于在氧化环境中使用对底层金属层的局部区域进行的激光烧蚀程序。 激光烧蚀过程仅在激光点产生所需的高温，允许在该温度下产生高K层，而不直接暴露于激光烧蚀过程的半导体衬底上的周围结构保持在较低温度 。 第二次迭代的特征在于在氧化环境中进行的底层金属层的特定区域到UV或I线曝光程序，暴露于UV或I线程序的下面的金属层的区域， 通过覆盖光刻板中的透明区域。 该过程还导致在下面的金属层的顶部上形成高K层。

公开(公告)号：US06486515B2

公开(公告)日：2002-11-26

申请号：US10131536

申请日：2002-04-24

申请人： Song Jun ,  Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek

发明人： Song Jun ,  Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek

IPC分类号： H01L2362

CPC分类号： H01L27/0251 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. An N-well is formed within a silicon semiconductor substrate. A P+ region is implanted within a portion of the N-well and an N+ region is implanted within a portion of the semiconductor substrate not occupied by the N-well. An oxide layer is formed overlying the semiconductor substrate and patterned to form openings to the semiconductor substrate. An epitaxial silicon layer is grown within the openings and overlying the oxide layer. Shallow trench isolation regions are formed within the epitaxial silicon layer extending to the underlying oxide layer. Gate electrodes and associated source and drain regions are formed in and on the epitaxial silicon layer between the shallow trench isolation regions. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. The interlevel dielectric layer is covered with a mask that covers the first contact openings. Second contact openings are opened through the interlevel dielectric layer, shallow trench isolations, and the oxide layer to the N+ region and P+ region. The mask is removed. The first and second contact openings are filled with a conducting layer to complete formation of an ESD device.

摘要翻译： 描述了使用绝缘体上硅技术形成静电放电装置的方法。 在硅半导体衬底内形成N阱。 将P +区注入到N阱的一部分内，并且将N +区注入到不被N阱占据的半导体衬底的一部分内。 在半导体衬底上形成氧化物层并图案化以形成到半导体衬底的开口。 外延硅层生长在开口内并覆盖氧化物层。 在延伸到下面的氧化物层的外延硅层内形成浅沟槽隔离区。 在浅沟槽隔离区域之间的外延硅层中和栅极电极和相关的源极和漏极区域上形成栅电极。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 用覆盖第一接触开口的掩模覆盖层间电介质层。 第二接触开口通过层间介质层，浅沟槽隔离层和氧化物层开放到N +区域和P +区域。 去除面具。 第一和第二接触开口填充有导电层以完成ESD装置的形成。

公开(公告)号：US06399431B1

公开(公告)日：2002-06-04

申请号：US09531786

申请日：2000-03-21

申请人： Jun Song ,  Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong

发明人： Jun Song ,  Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong

IPC分类号： H01L2170

CPC分类号： H01L21/84 ,  H01L27/0266 ,  H01L27/1203 ,  H01L29/78603

摘要： A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. A silicon-on-insulator substrate is provided comprising a semiconductor substrate underlying an oxide layer underlying a silicon layer. The silicon layer and oxide layer are patterned to form a gate electrode wherein the semiconductor substrate is exposed. Ions are implanted into the exposed semiconductor substrate to form source and drain regions adjacent to the gate electrode. Spacers are formed on sidewalls of the gate electrode. An interlevel dielectric layer is deposited overlying the gate electrode. Openings are formed through the interlevel dielectric layer to the source and drain regions and filled with a conducting layer. The conducting layer is patterned to form conducting lines to complete formation of an electrostatic discharge device using SOI technology in the fabrication of integrated circuits.

摘要翻译： 描述了使用绝缘体上硅技术形成静电放电装置的方法。 提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下方的半导体衬底。 图案化硅层和氧化物层以形成其中暴露半导体衬底的栅电极。 将离子注入到暴露的半导体衬底中以形成与栅电极相邻的源区和漏区。 隔板形成在栅电极的侧壁上。 沉积在栅电极上的层间电介质层。 开口通过层间介电层形成到源区和漏区，并填充有导电层。 图案化导电层以形成导线，以在集成电路的制造中使用SOI技术完成静电放电装置的形成。