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公开(公告)号：US11048421B2
公开(公告)日：2021-06-29
申请号：US17030392
申请日：2020-09-24
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang , Chun-Chieh Kuo , Ching-Hui Lin , Yang-Chih Shen
Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
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公开(公告)号：US10917119B2
公开(公告)日：2021-02-09
申请号：US16568221
申请日：2019-09-11
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Sheng-I Hsu
Abstract: A data storage system includes a processing circuit, a calculating circuit and an encoding circuit. The processing circuit receives a data byte from a host. The calculating circuit generates a cyclic redundancy check code according to an LBA, and combines the cyclic redundancy check code and the data byte into a data sector so that the data sector includes LBA-related information. The encoding circuit encodes the data sector to generate an error checking and correcting code, and combines the data sector and the error checking and correcting code into a storage data, so that the storage data includes the LBA-related information without including the LBA. Via the data sector and the storage data, the data storage system performs cyclic redundancy checking as well as error checking and correcting without storing the LBA for reducing 1-bit errors; and the LBA-related information does not include part or all of the LBA.
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公开(公告)号：US20210011643A1
公开(公告)日：2021-01-14
申请号：US17030392
申请日：2020-09-24
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang , Chun-Chieh Kuo , Ching-Hui Lin , Yang-Chih Shen
Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
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公开(公告)号：US10795835B2
公开(公告)日：2020-10-06
申请号：US16053764
申请日：2018-08-02
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang
Abstract: A storage device and an interface chip thereof are provided, wherein the interface chip can be applied to the storage device. The interface chip comprises a slave interface circuit, a master interface circuit, and a control circuit. The storage device comprises a memory controller and a non-volatile (NV) memory, and the NV memory comprises a plurality of NV memory chips. The slave interface circuit is arranged for coupling the interface chip to the memory controller. The master interface circuit is arranged for coupling the interface chip to a set of NV memory chips within the plurality of NV memory chips. A hierarchical architecture in the storage device comprises the memory controller, the interface chip, and the set of NV memory chips. The control circuit is arranged for controlling operations of the interface chip.
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公开(公告)号：US20200310666A1
公开(公告)日：2020-10-01
申请号：US16365695
申请日：2019-03-27
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Wen-Long Wang
Abstract: A method for performing data-accessing management in a storage server and associated apparatus such as a host device, a storage device, etc. are provided. The method includes: in response to a client request of writing a first set of data into the storage server, utilizing the host device within the storage server to trigger broadcasting an internal request corresponding to the client request toward each storage device of a plurality of storage devices within the storage server; and in response to the internal request corresponding to the client request, utilizing said each storage device of the plurality of storage devices to search for the first set of data in said each storage device to determine whether the first set of data has been stored in any storage device, for controlling the storage server completing the client request without duplication of the first set of data within the storage server.
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Patent Agency Ranking
公开(公告)号：US20200304148A1
公开(公告)日：2020-09-24
申请号：US16896210
申请日：2020-06-09
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang , Hong-Jung Hsu
Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
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公开(公告)号：US10713115B2
公开(公告)日：2020-07-14
申请号：US16184925
申请日：2018-11-08
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Hong-Jung Hsu , Jian-Dong Du
Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
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公开(公告)号：US20200051623A1
公开(公告)日：2020-02-13
申请号：US16656533
申请日：2019-10-17
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Hsiao-Te Chang , Wen-Long Wang
Abstract: A method for performing memory access includes: performing a first sensing operation corresponding to a first sensing voltage and performing at least a second sensing operation corresponding to a second sensing voltage to respectively generate a first digital value of a Flash cell of a Flash memory and a second digital value of the Flash cell of the Flash memory; using the first digital value, the second digital value, and charge distribution statistics information of the Flash memory to obtain soft information of a bit stored in the Flash cell, wherein the soft information corresponds to a threshold voltage of the Flash cell; and using the soft information to perform soft decoding.
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公开(公告)号：US20190121755A1
公开(公告)日：2019-04-25
申请号：US16048348
申请日：2018-07-30
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang
CPC classification number: G06F13/1668 , G06F11/1004 , G06F11/1012 , G06F11/1068 , G06F11/108 , G11C29/52
Abstract: A storage device and an interface chip thereof are provided, wherein the interface chip can be applied to the storage device. The interface chip comprises a slave interface circuit, a master interface circuit, and a control circuit. The storage device comprises a memory controller and a non-volatile (NV) memory, and the NV memory comprises a plurality of NV memory chips. The slave interface circuit is arranged for coupling the interface chip to the memory controller. The master interface circuit is arranged for coupling the interface chip to a set of NV memory chips within the plurality of NV memory chips. A hierarchical architecture in the storage device comprises the memory controller, the interface chip, and the set of NV memory chips. The control circuit is arranged for controlling operations of the interface chip.
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公开(公告)号：US20180285195A1
公开(公告)日：2018-10-04
申请号：US15997674
申请日：2018-06-04
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Hong-Jung Hsu , Jian-Dong Du
CPC classification number: G06F11/1068 , G06F11/1072 , G06F11/1076 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C29/52 , G11C2211/5641
Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
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