公开(公告)号：US20200335511A1

公开(公告)日：2020-10-22

申请号：US16919697

申请日：2020-07-02

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO ,  MARK REITEN

IPC: H01L27/11531 ,  G06N3/08 ,  G11C16/04 ,  H01L29/788

Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：US20230259738A1

公开(公告)日：2023-08-17

申请号：US18141090

申请日：2023-04-28

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Hieu Van Tran ,  NHAN DO ,  FARNOOD MERRIKH BAYAT ,  XINJIE GUO ,  DMITRI STRUKOV ,  VIPIN TIWARI ,  MARK REITEN

IPC: G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/34 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/06

CPC classification number: G06N3/04 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06N3/045 ,  G06N3/063 ,  G11C11/54 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3436 ,  G11C29/38

Abstract: A memory device includes a non-volatile memory cells, source regions and drain regions arranged in rows and columns. Respective ones of the columns of drain regions include first drain regions and second drain regions that alternate with each other. Respective ones of first lines electrically connect together the source regions in one of the rows of the source regions and are electrically isolated from the source regions in other rows of the source regions. Respective ones of second lines electrically connect together the first drain regions of one of the columns of drain regions and are electrically isolated from the second drain regions of the one column of drain regions. Respective ones of third lines electrically connect together the second drain regions of one of the columns of drain regions and are electrically isolated from the first drain regions of the one column of drain regions.

公开(公告)号：US20220147794A1

公开(公告)日：2022-05-12

申请号：US17580862

申请日：2022-01-21

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： FARNOOD MERRIKH BAYAT ,  XINJIE GUO ,  DMITRI STRUKOV ,  NHAN DO ,  HIEU VAN TRAN ,  VIPIN TIWARI ,  MARK REITEN

IPC: G06N3/04 ,  G06N3/063 ,  G06F3/06

Abstract: An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs.

公开(公告)号：US20210358551A1

公开(公告)日：2021-11-18

申请号：US17082956

申请日：2020-10-28

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  STANLEY HONG ,  STEPHEN TRINH ,  THUAN VU ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G11C16/34 ,  G11C11/56 ,  G06N3/063

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Two or more physical memory cells are grouped together to form a logical cell that stores one of N possible levels. Within each logical cell, the memory cells can be programmed using different mechanisms. For example, one or more of the memory cells in a logical cell can be programmed using a coarse programming mechanism, one or more of the memory cells can be programmed using a fine mechanism, and one or more of the memory cells can be programmed using a tuning mechanism. This achieves extreme programming accuracy and programming speed.

公开(公告)号：US20210295907A1

公开(公告)日：2021-09-23

申请号：US17024410

申请日：2020-09-17

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  THUAN VU ,  STEPHEN TRINH ,  STANLEY HONG ,  ANH LY ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G06N3/063

Abstract: Numerous embodiments for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. High voltage circuits used to generate high voltages applied to terminals of the non-volatile memory cells during the precision tuning process are also disclosed. Programming sequences for the application of the voltages to the terminals to minimize the occurrence of disturbances during tuning are also disclosed.

公开(公告)号：US20210232893A1

公开(公告)日：2021-07-29

申请号：US17233006

申请日：2021-04-16

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： FARNOOD MERRIKH BAYAT ,  XINJIE GUO ,  DMITRI STRUKOV ,  NHAN DO ,  HIEU VAN TRAN ,  VIPIN TIWARI ,  MARK REITEN

IPC: G06N3/04 ,  G06N3/063 ,  G06F3/06

Abstract: Numerous embodiments are disclosed for verifying a weight programmed into a selected non-volatile memory cell in a neural memory. In one embodiment, a circuit for verifying a weight programmed into a selected non-volatile memory cell in a neural memory comprises a converter for converting a target weight into a target current and a comparator for comparing the target current to an output current from the selected non-volatile memory cell during a verify operation. In another embodiment, a circuit for verifying a weight programmed into a selected non-volatile memory cell in a neural memory comprises a digital-to-analog converter for converting a target weight comprising digital bits into a target voltage, a current-to-voltage converter for converting an output current from the selected non-volatile memory cell during a verify operation into an output voltage, and a comparator for comparing the output voltage to the target voltage during a verify operation.

公开(公告)号：US20200349421A1

公开(公告)日：2020-11-05

申请号：US16449201

申请日：2019-06-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STEPHEN TRINH ,  THUAN VU ,  STANLEY HONG ,  VIPIN TIWARI ,  MARK REITEN ,  NHAN DO

IPC: G06N3/063 ,  G11C16/04 ,  G11C11/54 ,  G06F17/16

Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks.

公开(公告)号：US20190080767A1

公开(公告)日：2019-03-14

申请号：US16025039

申请日：2018-07-02

Applicant: Silicon Storage Technology, Inc.

Inventor： VIPIN TIWARI ,  NHAN DO

IPC: G11C16/10 ,  G11C16/28

Abstract: A memory device that includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines each connected to one of the columns of memory cells, and a plurality of differential sense amplifiers each having first and second inputs and an output. For each of the differential sense amplifiers, the differential sense amplifier is configured to generate an output signal on the output having an amplitude that is based upon a difference in signal amplitudes on the first and second inputs, the first input is connected to one of the bit lines, and the second input is connected to another one of the bit lines. Alternately, one or more sense amplifiers are configured to detect signal amplitudes on the bit lines, and the device includes calculation circuitry configured to produce output signals each based upon a difference in signal amplitudes on two of the bit lines.