公开(公告)号：US07279405B2

公开(公告)日：2007-10-09

申请号：US10980232

申请日：2004-11-04

申请人： Takaharu Itani ,  Takayuki Ito ,  Kyoichi Suguro

发明人： Takaharu Itani ,  Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/425

CPC分类号： H01L21/26533 ,  H01L21/324 ,  H01L29/6659

摘要： A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion maybe controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.

摘要翻译： 通过退火形成具有注入离子的高激活速率，低电阻率和受控的漏电流的浅p-n结扩散层。 通过光照射进行杂质掺杂后的退火。 这些杂质通过在将杂质掺杂到半导体衬底11之后通过光照射退火至少两次来激活。光辐射的特征在于使用W卤素灯RTA或闪光灯FLA，除了使用闪光灯FLA的最终光照射 。 杂质扩散可以被控制到最小，并且当在MOSFET的源极和漏极延伸区域中形成离子注入层时，在杂质掺杂过程中已经发展出的晶体缺陷可以被充分地减小，或者源中的离子注入层和 漏区。

公开(公告)号：US20070215918A1

公开(公告)日：2007-09-20

申请号：US11704924

申请日：2007-02-12

申请人： Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

发明人： Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

IPC分类号： H01L29/76

CPC分类号： H01L21/823857 ,  H01L21/823814 ,  H01L21/823842

摘要： A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.

摘要翻译： 半导体器件包括半导体区域，源极区域，漏极区域，源极延伸区域，漏极延伸区域，第一栅极绝缘膜，第二栅极绝缘膜和栅极电极。 源极区域，漏极区域，源极延伸区域和漏极延伸区域形成在半导体区域的表面部分中。 第一栅极绝缘膜形成在源极延伸区域和漏极延伸区域之间的半导体区域上。 第一栅极绝缘膜由氮浓度为15原子％以下的氧化硅膜或氮氧化硅膜形成。 第二栅极绝缘膜形成在第一栅极绝缘膜上，并且含有浓度为20原子％至57原子％之间的氮。 栅电极形成在第二栅绝缘膜上。

公开(公告)号：US20070166977A1

公开(公告)日：2007-07-19

申请号：US11644887

申请日：2006-12-26

申请人： Hiroshi Itokawa ,  Yoshimasa Kawase ,  Toshihiko Iinuma ,  Haruko Akutsu ,  Kyoichi Suguro

发明人： Hiroshi Itokawa ,  Yoshimasa Kawase ,  Toshihiko Iinuma ,  Haruko Akutsu ,  Kyoichi Suguro

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

摘要： A semiconductor device manufacturing method is disclosed. A silicon-containing gate electrode is first formed above the surface of a silicon-containing semiconductor substrate. Then, a sidewall insulating film is formed on the sidewall of the gate electrode and a film of metal is formed on the semiconductor substrate to cover the gate electrode and the sidewall insulating film. The front and back sides of the semiconductor substrate are heated through heat conduction by an ambient gas. Thereby, the metal is caused to react with silicon contained in the semiconductor substrate and the gate electrode to form a metal silicide film.

摘要翻译： 公开了半导体器件制造方法。 首先在含硅半导体衬底的表面上形成含硅栅电极。 然后，在栅电极的侧壁上形成侧壁绝缘膜，并且在半导体衬底上形成金属膜以覆盖栅电极和侧壁绝缘膜。 通过环境气体的热传导来加热半导体衬底的正面和背面。 由此，使金属与包含在半导体衬底和栅电极中的硅反应，形成金属硅化物膜。

公开(公告)号：US20070052039A1

公开(公告)日：2007-03-08

申请号：US11512187

申请日：2006-08-30

申请人： Toshihiko Iinuma ,  Haruko Akutsu ,  Kyoichi Suguro

发明人： Toshihiko Iinuma ,  Haruko Akutsu ,  Kyoichi Suguro

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L23/48 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a silicon region including Si, and a silicide film provided on the silicon region, the silicide film comprising a compound of Si with Ni, Co, Pd, or Pt and including Er.

摘要翻译： 半导体器件包括包含Si的硅区域和设置在硅区域上的硅化物膜，该硅化物膜包含Si与Ni，Co，Pd或Pt的化合物并包括Er的化合物。

公开(公告)号：US07157340B2

公开(公告)日：2007-01-02

申请号：US11052861

申请日：2005-02-09

申请人： Takayuki Ito ,  Kyoichi Suguro ,  Kanna Tomiie ,  Kazuya Ouchi

发明人： Takayuki Ito ,  Kyoichi Suguro ,  Kanna Tomiie ,  Kazuya Ouchi

IPC分类号： H01L21/336 ,  H01L21/331 ,  H01L21/332

CPC分类号： H01L21/823814 ,  H01L21/26513 ,  H01L21/2686 ,  H01L29/6659

摘要： A manufacturing method of a semiconductor device, the method including implanting impurity ions into a silicon layer and irradiating a pulsed light having a pulse width of 100 milliseconds or less and a rise time of 0.3 milliseconds or more onto the silicon layer thereby activating the impurity ions. The rise time is defined as a time interval of a leading edge between an instant at which the pulsed light starts to rise and an instant at which the pulsed light reaches a peak energy.

摘要翻译： 一种半导体器件的制造方法，所述方法包括将杂质离子注入到硅层中，并将脉冲宽度为100毫秒或更短的脉冲光和0.3毫秒或更长的上升时间照射到硅层上，从而激活杂质离子 。 上升时间被定义为脉冲光开始上升的瞬间与脉冲光达到峰值能量的瞬间之间的前沿的时间间隔。

公开(公告)号：US07122448B2

公开(公告)日：2006-10-17

申请号：US10926306

申请日：2004-08-26

申请人： Takayuki Ito ,  Kyoichi Suguro

发明人： Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/301 ,  H01L21/326

CPC分类号： H01L21/67115 ,  H01L21/26513 ,  H01L21/324

摘要： An annealing apparatus, includes a substrate stage placing a semiconductor substrate; a light source facing the substrate stage, configured to irradiate a pulsed light at a pulse width of approximately 0.1 ms to 100 ms on a surface of the semiconductor substrate; and a mask configured to selectively reduce intensity of the light transmitting a peripheral region along an outer edge of the semiconductor substrate, so as to define an irradiation region by the peripheral region.

摘要翻译： 退火设备包括：放置半导体衬底的衬底台; 面对所述衬底台的光源，被配置为在所述半导体衬底的表面上照射约0.1ms至100ms的脉冲宽度的脉冲光; 以及掩模，其被配置为选择性地降低沿着半导体衬底的外边缘传输周边区域的光的强度，以便通过周边区域限定照射区域。

公开(公告)号：US20050227463A1

公开(公告)日：2005-10-13

申请号：US11097259

申请日：2005-04-04

申请人： Takayuki Ito ,  Kyoichi Suguro

发明人： Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/336 ,  H01L21/425 ,  H01L21/8238

CPC分类号： H01L21/2236 ,  H01L21/823814 ,  Y10S438/918 ,  Y10S438/964

摘要： A doping method includes implanting first impurity ions into a semiconductor substrate, so as to form a damaged region in the vicinity of a surface of the semiconductor substrate, the first impurity ions not contributing to electric conductivity; implanting second impurity ions into the semiconductor substrate through the damaged region, the second impurity ions having an atomic weight larger than the first impurity ions and contributing to the electric conductivity; and heating the surface of the semiconductor substrate with a light having a pulse width of about 0.1 ms to about 100 ms, so as to activate the second impurity ions.

摘要翻译： 掺杂方法包括将第一杂质离子注入到半导体衬底中，以在半导体衬底的表面附近形成损伤区域，不对导电性有贡献的第一杂质离子; 通过损伤区域将第二杂质离子注入到半导体衬底中，第二杂质离子的原子量大于第一杂质离子并有助于导电性; 并用脉冲宽度为约0.1ms至约100ms的光来加热半导体衬底的表面，以激活第二杂质离子。

公开(公告)号：US06825597B2

公开(公告)日：2004-11-30

申请号：US10301675

申请日：2002-11-22

申请人： Kyoichi Suguro

发明人： Kyoichi Suguro

IPC分类号： H01J3708

CPC分类号： H01J27/14 ,  H01J37/08 ,  H01J2237/31701

摘要： This ion source includes a chamber having an internal wall surface and an external wall surface, and also includes a cathode, which is provided to be insulated from the chamber, capable of emitting thermal electrons into the chamber, and has a cathode cap protruding into the chamber from an external side of an opening part which is formed to pass through from the external wall surface to the internal wall surface of the chamber and a filament disposed inside the cathode cap, the cathode cap and/or the filament being an alloy containing tungsten (W) as a major component and a predetermined metal element as a minor component.

摘要翻译： 该离子源包括具有内壁表面和外壁表面的室，并且还包括阴极，该阴极被提供以与室绝缘，能够将热电子发射到室中，并且具有突出到阴极盖中的阴极帽 腔室，其从形成为从外壁表面通过的开口部分的外侧延伸到腔室的内壁表面;以及细丝，其设置在阴极帽内部，阴极帽和/或细丝为含有钨的合金 （W）作为主要成分，预定的金属元素作为次要成分。

公开(公告)号：US06730581B2

公开(公告)日：2004-05-04

申请号：US09877136

申请日：2001-06-11

申请人： Kyoichi Suguro

发明人： Kyoichi Suguro

IPC分类号： H01L2120

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/2822 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/94

摘要： Variations in threshold voltage among MOS devices are prevented by forming a metal gate electrode having an average grain size of 30 nm or less on a gate insulating film.

摘要翻译： 通过在栅极绝缘膜上形成平均粒径为30nm以下的金属栅电极来防止MOS器件之间的阈值电压的变化。

公开(公告)号：US06482714B1

公开(公告)日：2002-11-19

申请号：US09512320

申请日：2000-02-24

申请人： Katsuhiko Hieda ,  Kyoichi Suguro

发明人： Katsuhiko Hieda ,  Kyoichi Suguro

IPC分类号： H01C2176

CPC分类号： H01L29/517 ,  H01L21/28061 ,  H01L21/28079 ,  H01L21/28211 ,  H01L21/28238 ,  H01L21/324 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665

摘要： Disclosed is a semiconductor device comprising a transistor structure including an epitaxial silicon layer formed on a main surface of an n-type semiconductor substrate, source-drain diffusion layers formed on at least the epitaxial silicon layer, a channel region formed between the source and drain regions, and a gate electrode formed on the channel region with a gate insulating film interposed therebetween, an element isolation region being sandwiched between adjacent transistor structures, wherein a punch-through stopper layer formed in a lower portion of the channel region has an impurity concentration higher than that of the channel region, and the source-drain diffusion layers do not extend to overlap with edge portion of insulating films for the element isolation.

摘要翻译： 公开了一种半导体器件，包括晶体管结构，其包括在n型半导体衬底的主表面上形成的外延硅层，至少形成在外延硅层上的源极 - 漏极扩散层，形成在源极和漏极之间的沟道区 区域，以及形成在沟道区上的栅电极，隔着栅绝缘膜的元件隔离区域夹在相邻的晶体管结构之间，其中形成在沟道区的下部的穿通阻挡层具有杂质浓度 高于沟道区域，并且源极 - 漏极扩散层不延伸以与用于元件隔离的绝缘膜的边缘部分重叠。