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11.发明授权公开(公告)号：US07380052B2
公开(公告)日：2008-05-27
申请号：US10992378
申请日：2004-11-18
IPC分类号： G06F12/00
CPC分类号： G11C29/02 , G11C29/022 , G11C29/028
摘要： A method, an apparatus, and a computer program are provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for the calibration patterns. However, there are different procedures and requirements for transmission and reception calibrations. Hence, to reduce the amount of hardware needed to perform transmission and reception calibrations, the data buffers employ additional front end circuitry to reuse the buffers for both tasks.
摘要翻译： 提供了一种方法，装置和计算机程序来重用功能数据缓冲器。 使用极限数据速率（XDR（TMDR））动态随机存取存储器（DRAM），采用测试模式来动态校准数据与时钟。 为了执行此任务，采用数据缓冲器来存储校准模式的数据和命令。 然而，发送和接收校准有不同的程序和要求。 因此，为了减少执行发送和接收校准所需的硬件数量，数据缓冲器使用附加的前端电路来为这两个任务重新使用缓冲器。
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12.发明授权Method and apparatus for generating a mask value and command for extreme data rate memories utilizing error correction codes 有权用于利用纠错码生成用于极端数据速率存储器的掩码值和命令的方法和装置公开(公告)号：US07287103B2
公开(公告)日：2007-10-23
申请号：US11130911
申请日：2005-05-17
CPC分类号： G11C7/1006
摘要： A method, an apparatus, and a computer program product are provided for the handling of write mask operations in an XDR™ DRAM memory system. This invention eliminates the need for a two-port array because the mask generation is done as the data is received. Less logic is needed for the mask calculation because only 144 of the 256 possible byte values are decoded. The mask value is generated and stored in a mask array. Independently, the write data is stored in a write buffer. The mask value is utilized to generate a write mask command. Once the write mask command is issued, the write data and the mask value are transmitted to a multiplexer. The multiplexer masks the write data using the mask value, so that the masked data can be stored in the XDR DRAMS.
摘要翻译： 提供了一种方法，装置和计算机程序产品，用于处理XDR（TM）DRAM存储器系统中的写掩码操作。 本发明消除了对双端口阵列的需要，因为在接收到数据时完成了掩码生成。 掩码计算需要较少的逻辑，因为256个可能的字节值中只有144个被解码。 掩码值生成并存储在掩码数组中。 独立地，写入数据被存储在写入缓冲器中。 掩码值用于生成写掩码命令。 一旦写掩码命令被发出，写入数据和掩码值被发送到多路复用器。 多路器使用掩码值对写入数据进行掩码，以便将掩蔽的数据存储在XDR DRAMS中。
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13.发明授权Method, apparatus, and computer program product for implementing packet ordering 有权用于实现分组排序的方法，装置和计算机程序产品公开(公告)号：US07248595B2
公开(公告)日：2007-07-24
申请号：US10624351
申请日：2003-07-22
IPC分类号： H04L12/56
CPC分类号： H04L49/9094 , H04L49/90
摘要： A method, apparatus, and computer program product are provided for implementing packet ordering in a network processor. Packets are received and placed on a receive queue and a queue entry is provided for each received packet. The queue entry includes for each autoroute packet, an autoroute indication and a selected transmit queue. An associated ordering queue is provided with the receive queue. A software-handled packet is dequeued from the receive queue and the dequeued software-handled packet is placed on the ordering queue. Each autoroute packet reaching a head of the receive queue is automatically moved to the selected ordering queue.
摘要翻译： 提供了一种在网络处理器中实现分组排序的方法，装置和计算机程序产品。 数据包被接收并放置在接收队列上，并为每个接收到的数据包提供队列条目。 队列条目包括每个自动路由分组，自动路由指示和所选择的发送队列。 与接收队列一起提供相关联的排队队列。 软件处理的数据包从接收队列出队，出队的软件处理的数据包放在排队队列上。 到达接收队列头部的每个自动路由分组被自动移动到所选择的排队队列。
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14.发明授权公开(公告)号：US07925823B2
公开(公告)日：2011-04-12
申请号：US11875469
申请日：2007-10-19
IPC分类号： G06F12/00
CPC分类号： G11C29/02 , G11C29/022 , G11C29/028
摘要： A mechanism is provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for the calibration patterns. However, there are different procedures and requirements for transmission and reception calibrations. Hence, to reduce the amount of hardware needed to perform transmission and reception calibrations, the data buffers employ additional front end circuitry to reuse the buffers for both tasks.
摘要翻译： 提供了重用功能数据缓冲器的机制。 使用极限数据速率（XDR™）动态随机存取存储器（DRAM），采用测试模式来动态校准数据与时钟。 为了执行此任务，采用数据缓冲器来存储校准模式的数据和命令。 然而，发送和接收校准有不同的程序和要求。 因此，为了减少执行发送和接收校准所需的硬件数量，数据缓冲器使用附加的前端电路来为这两个任务重新使用缓冲器。
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15.发明授权Managing write-to-read turnarounds in an early read after write memory system 有权在写入内存系统之后的早期读取中管理写入阅读的周转时间公开(公告)号：US07752379B2
公开(公告)日：2010-07-06
申请号：US12349240
申请日：2009-01-06
申请人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Tolga Ozguner
发明人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Tolga Ozguner
CPC分类号： G06F13/161 , G06F13/1647
摘要： Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.
摘要翻译： 介绍了在写入内存系统之后的早期读取中管理写入阅读的周转时间。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信号 一个奇怪的DRAM银行。
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公开(公告)号：US07676639B2
公开(公告)日：2010-03-09
申请号：US12034681
申请日：2008-02-21
IPC分类号： G06F12/00
CPC分类号： G06F13/1673 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834
摘要： Separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system is provided. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.
摘要翻译： 提供了在XDR™存储系统中单独处理读写修改写命令的读写操作。 本发明允许系统在RMW的读取和写入之间发出其他命令。 这确保从读取到写入的数据流时间不是一个惩罚。 使用RMW缓冲器来存储读取的数据，并且使用写入缓冲器来存储写入数据。 使用MUX来合并读取数据和写入数据，并通过XIO将合并的数据发送到目标DRAM。 RMW缓冲区也可用于擦除命令。
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公开(公告)号：US20080148108A1
公开(公告)日：2008-06-19
申请号：US12033910
申请日：2008-02-20
CPC分类号： G06F13/1673 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834
摘要： Separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system is provided. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.
摘要翻译： 提供了在XDR（TM）存储器系统中单独处理读取 - 修改 - 写入命令的读取和写入操作。 本发明允许系统在RMW的读取和写入之间发出其他命令。 这确保从读取到写入的数据流时间不是一个惩罚。 使用RMW缓冲器来存储读取的数据，并且使用写入缓冲器来存储写入数据。 使用MUX来合并读取数据和写入数据，并通过XIO将合并的数据发送到目标DRAM。 RMW缓冲区也可用于擦除命令。
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18.发明授权Method and apparatus for implementing packet work area accesses and buffer sharing 有权用于实现分组工作区访问和缓冲区共享的方法和装置公开(公告)号：US07240166B2
公开(公告)日：2007-07-03
申请号：US10427864
申请日：2003-05-01
申请人： Paul Allen Ganfield
发明人： Paul Allen Ganfield
CPC分类号： H04L49/901 , G06F12/1027 , H04L49/90 , H04L49/9021
摘要： A mapping area including a packet work area and a corresponding set of packet segment registers are provided. A packet segment register is loaded with a Packet ID (PID) and a packet translation unit maps packet data into the corresponding packet work area. Packets include one or more data buffers. Data buffers are chained together using a corresponding buffer descriptor for each data buffer. Each buffer descriptor points to the corresponding data buffer and to a next buffer descriptor. Each buffer descriptor includes an offset for a next packet data. A translate address is compared to the offset of each buffer descriptor to identify the data buffer containing the translate address. A buffer sharing counter (BSC) is allocated for a shared data buffer. Each buffer descriptor pointing to the shared data includes a pointer to the buffer sharing counter (BSC).
摘要翻译： 提供了包括分组工作区域和相应的分组段寄存器组的映射区域。 分组段寄存器装载有分组ID（PID），并且分组转换单元将分组数据映射到相应的分组工作区域中。 数据包包括一个或多个数据缓冲区。 数据缓冲区使用每个数据缓冲区的相应缓冲区描述符链接在一起。 每个缓冲区描述符指向相应的数据缓冲区和下一个缓冲区描述符。 每个缓冲器描述符包括下一个分组数据的偏移量。 将翻译地址与每个缓冲区描述符的偏移进行比较，以识别包含翻译地址的数据缓冲区。 为共享数据缓冲区分配缓冲区共享计数器（BSC）。 指向共享数据的每个缓冲描述符包括指向缓冲区共享计数器（BSC）的指针。
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19.发明授权Data strobe signals (DQS) for high speed dynamic random access memories (DRAMs) 失效用于高速动态随机存取存储器（DRAM）的数据选通信号（DQS）公开(公告)号：US06909315B2
公开(公告)日：2005-06-21
申请号：US10102274
申请日：2002-03-20
IPC分类号： G11C7/10 , G11C7/22 , G11C11/4076 , G11C29/02 , H03H11/26
CPC分类号： G11C29/028 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C11/401 , G11C11/4076 , G11C29/02 , G11C29/50012 , G11C2207/2254
摘要： Embodiments are provided in which a method for delaying a strobe signal for a first pre-specified amount of time is described. A test signal is sent through a first number of delay books and a test is done as to whether it takes the test signal approximately a second pre-specified amount of time to pass the first number of delay books. Then, the number of delay books is increased or decreased by one at a time and until the number of delay books reaches a second number where it takes the test signal approximately the second pre-specified amount of time to pass the second number of delay books. From the second number, a third number of delay books is determined which is needed to cause a propagation delay approximately equal to the first pre-specified amount of time. Finally, the strobe signal is passed through the third number of delay books.
摘要翻译： 提供了一种用于延迟第一预定时间量的选通信号的方法的实施例。 通过第一数量的延迟书发送测试信号，并且测试是否将测试信号大约第二预定的时间量通过第一数量的延迟书。 然后，延迟书的数量一次增加或减少，直到延迟书的数量达到第二个数字，其中测试信号大约第二个预定的时间量通过第二数量的延迟书 。 从第二个数字，确定第三数量的延迟书，其需要使传播延迟大致等于第一预先指定的时间量。 最后，频闪信号通过第三数量的延迟书。
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20.发明授权Method and apparatus for handling variable data word widths and array depths in a serial shared abist scheme 失效用于处理串行共享静态方案中可变数据字宽和阵列深度的方法和装置
公开(公告)号：US5835502A
公开(公告)日：1998-11-10
申请号：US673258
申请日：1996-06-28
申请人： Anthony Gus Aipperspach , Todd Alan Christensen , Leland Leslie Day , Paul Allen Ganfield , Murali Vaddigiri , Paul Wong
发明人： Anthony Gus Aipperspach , Todd Alan Christensen , Leland Leslie Day , Paul Allen Ganfield , Murali Vaddigiri , Paul Wong
CPC分类号： G11C29/32
摘要： A method and apparatus for handling variable data word widths and array depths in an array built-in self-test system for testing a plurality of memory arrays using a single controller. Each array includes a predetermined row and column address depth and data word width. Each array further includes a scan register. A universal test data word is generated and sent to the scan register of each array. The universal length test data word has a length dependent upon the maximum row address depth, maximum column address depth and/or the maximum data word width. A portion of the test data word which exceeds the column address depth, row address depth and/or the data word width of a particular array is shifted off the end of the scan register of the particular array.
摘要翻译： 一种用于处理阵列内置自检系统中的可变数据字宽度和阵列深度的方法和装置，用于使用单个控制器来测试多个存储器阵列。 每个阵列包括预定的行和列地址深度和数据字宽度。 每个阵列还包括扫描寄存器。 生成通用测试数据字并将其发送到每个阵列的扫描寄存器。 通用长度测试数据字的长度取决于最大行地址深度，最大列地址深度和/或最大数据字宽度。 超过特定阵列的列地址深度，行地址深度和/或数据字宽度的测试数据字的一部分从特定阵列的扫描寄存器的结尾偏移。
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