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    Data strobe signals (DQS) for high speed dynamic random access memories (DRAMs)
    1.
    发明授权
    Data strobe signals (DQS) for high speed dynamic random access memories (DRAMs) 失效
    用于高速动态随机存取存储器（DRAM）的数据选通信号（DQS）

    公开(公告)号：US06909315B2

    公开(公告)日：2005-06-21

    申请号：US10102274

    申请日：2002-03-20

    申请人： Michael Frank Carnevale ,  Paul Allen Ganfield ,  Daniel Frank Moertl

    发明人： Michael Frank Carnevale ,  Paul Allen Ganfield ,  Daniel Frank Moertl

    IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C29/02 ,  H03H11/26

    CPC分类号： G11C29/028 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/50012 ,  G11C2207/2254

    摘要： Embodiments are provided in which a method for delaying a strobe signal for a first pre-specified amount of time is described. A test signal is sent through a first number of delay books and a test is done as to whether it takes the test signal approximately a second pre-specified amount of time to pass the first number of delay books. Then, the number of delay books is increased or decreased by one at a time and until the number of delay books reaches a second number where it takes the test signal approximately the second pre-specified amount of time to pass the second number of delay books. From the second number, a third number of delay books is determined which is needed to cause a propagation delay approximately equal to the first pre-specified amount of time. Finally, the strobe signal is passed through the third number of delay books.

    摘要翻译： 提供了一种用于延迟第一预定时间量的选通信号的方法的实施例。 通过第一数量的延迟书发送测试信号，并且测试是否将测试信号大约第二预定的时间量通过第一数量的延迟书。 然后，延迟书的数量一次增加或减少，直到延迟书的数量达到第二个数字，其中测试信号大约第二个预定的时间量通过第二数量的延迟书 。 从第二个数字，确定第三数量的延迟书，其需要使传播延迟大致等于第一预先指定的时间量。 最后，频闪信号通过第三数量的延迟书。

    Method and apparatus for managing write-to-read turnarounds in an early read after write memory system
    2.
    发明授权
    Method and apparatus for managing write-to-read turnarounds in an early read after write memory system 有权
    用于在写入存储器系统之后的早期读取中管理写入读取周转的方法和装置

    公开(公告)号：US07321950B2

    公开(公告)日：2008-01-22

    申请号：US11050021

    申请日：2005-02-03

    申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

    IPC分类号： G06F12/00

    CPC分类号： G06F13/161 ,  G06F13/1647

    摘要： A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

    摘要翻译： 提出了一种用于在写入存储器系统之后的早期读取中管理写入到读取周转的方法和装置。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

    Managing write-to-read turnarounds in an early read after write memory system
    3.
    发明授权
    Managing write-to-read turnarounds in an early read after write memory system 有权
    在写入内存系统之后的早期读取中管理写入阅读的周转时间

    公开(公告)号：US07487318B2

    公开(公告)日：2009-02-03

    申请号：US11851468

    申请日：2007-09-07

    申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F13/161 ,  G06F13/1647

    摘要： Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

    摘要翻译： 介绍了在写入内存系统之后的早期读取中管理写入阅读的周转时间。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

    Memory controller operating in a system with a variable system clock
    4.
    发明授权
    Memory controller operating in a system with a variable system clock 有权
    内存控制器在具有可变系统时钟的系统中运行

    公开(公告)号：US07467277B2

    公开(公告)日：2008-12-16

    申请号：US11348879

    申请日：2006-02-07

    申请人： Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

    发明人： Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

    IPC分类号： G06F13/14

    CPC分类号： G11C8/18 ,  G06F13/1642 ,  G06F13/1689 ,  Y02D10/14

    摘要： The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

    摘要翻译： 本发明一般涉及在包含可变系统时钟的系统中操作的存储器控​​制器。 存储器控制器可以与以可变处理器时钟频率工作的处理器交换数据。 然而，存储器控制器可以以恒定的存储器时钟频率执行存储器访问。 可以提供异步缓冲器以跨可变和恒定时钟域传输数据。 为了防止在切换到较低处理器时钟频率时读取缓冲区溢出，存储器控制器可以使存储器定序器静止，并以较慢的速率从定序器调速读取数据。 为了防止在运行中写入数据，存储器控制器的数据流逻辑可以执行握手以确保在执行写访问之前在缓冲器中完全接收到写数据。

    Methods and Apparatus for Interfacing a Processor and a Memory
    5.
    发明申请
    Methods and Apparatus for Interfacing a Processor and a Memory 审中-公开
    用于接口处理器和存储器的方法和装置

    公开(公告)号：US20080168206A1

    公开(公告)日：2008-07-10

    申请号：US11620110

    申请日：2007-01-05

    申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

    IPC分类号： G06F13/14

    CPC分类号： G06F13/4059

    摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a computer system including (a) a first memory; (b) a processor adapted to issue a functional command to the first memory; (c) a translation chip; (d) a cache memory coupled to the translation chip; (e) a first link adapted to couple the processor to the translation chip; and (f) a second link adapted to couple the translation chip to the first memory; and (2) calibrating the first link to transmit data between the processor and cache memory. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供一种包括（a）第一存储器的计算机系统; （b）适于向第一存储器发出功能命令的处理器; （c）翻译芯片; （d）耦合到所述平移芯片的高速缓冲存储器; （e）适于将所述处理器耦合到所述翻译芯片的第一链接; 和（f）适于将所述翻译芯片耦合到所述第一存储器的第二链路; 和（2）校准第一链路以在处理器和高速缓冲存储器之间传送数据。 提供了许多其他方面。

    Using Extreme Data Rate Memory Commands to Scrub and Refresh Double Data Rate Memory
    7.
    发明申请
    Using Extreme Data Rate Memory Commands to Scrub and Refresh Double Data Rate Memory 审中-公开
    使用极限数据速率存储器命令来刷新和刷新双倍数据速率存储器

    公开(公告)号：US20080183916A1

    公开(公告)日：2008-07-31

    申请号：US11668531

    申请日：2007-01-30

    申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Ryan Abel Heckendorf ,  John David Irish ,  David Alan Norgaard ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Ryan Abel Heckendorf ,  John David Irish ,  David Alan Norgaard ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

    IPC分类号： G06F13/00

    CPC分类号： G06F11/106

    摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a processor adapted to issue a command complying with a first protocol; (2) providing a memory coupled to the processor and accessible by a command complying with a second protocol; (3) employing a plurality of scrub commands complying with the second protocol to check respective portions of the memory for errors, wherein each scrub command complying with the second protocol is a converted version of a scrub command complying with the first protocol issued by the processor and the respective portions are non-sequential; and (4) refreshing bits stored in the entire memory within a predetermined time period. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供适于发出符合第一协议的命令的处理器; （2）提供耦合到所述处理器的存储器，并且可通过符合第二协议的命令来访问; （3）采用符合第二协议的多个擦除命令来检查存储器的相应部分的错误，其中符合第二协议的每个擦除命令是符合由处理器发出的第一协议的擦除命令的转换版本 并且各部分是非顺序的; 和（4）在预定时间段内刷新存储在整个存储器中的位。 提供了许多其他方面。

    Methods and Apparatus for Calibrating Heterogeneous Memory Interfaces
    8.
    发明申请
    Methods and Apparatus for Calibrating Heterogeneous Memory Interfaces 审中-公开
    用于校准异构存储器接口的方法和装置

    公开(公告)号：US20080168298A1

    公开(公告)日：2008-07-10

    申请号：US11620104

    申请日：2007-01-05

    申请人： Mark David Bellows ,  Paul Allen Ganfield ,  David Alan Norgaard ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Paul Allen Ganfield ,  David Alan Norgaard ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

    IPC分类号： G06F12/00 ,  G06F1/08

    CPC分类号： G11C7/10 ,  G11C2207/2254

    摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a computer system including (a) a memory; (b) a processor adapted to issue a functional command to the memory; (c) a translation chip; (d) a first link adapted to couple the processor to the translation chip; and (e) a second link adapted to couple the translation chip to the memory; (2) calibrating the first link using the translation chip; and (3) while calibrating the first link, calibrating the second link using the translation chip. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供一种包括（a）存储器的计算机系统; （b）适于向存储器发出功能命令的处理器; （c）翻译芯片; （d）适于将所述处理器耦合到所述翻译芯片的第一链接; 和（e）适于将所述翻译芯片耦合到所述存储器的第二链接; （2）使用翻译芯片校准第一链接; 和（3）在校准第一链路的同时，使用转换芯片校准第二链路。 提供了许多其他方面。

    Reuse of functional data buffers for pattern buffers in XDR DRAM
    9.
    发明授权
    Reuse of functional data buffers for pattern buffers in XDR DRAM 失效
    在XDR DRAM中重用图形缓冲区的功能数据缓冲区

    公开(公告)号：US07380052B2

    公开(公告)日：2008-05-27

    申请号：US10992378

    申请日：2004-11-18

    申请人： Mark David Bellows ,  Kent Harold Haselhorst ,  Paul Allen Ganfield ,  Tolga Ozguner

    发明人： Mark David Bellows ,  Kent Harold Haselhorst ,  Paul Allen Ganfield ,  Tolga Ozguner

    IPC分类号： G06F12/00

    CPC分类号： G11C29/02 ,  G11C29/022 ,  G11C29/028

    摘要： A method, an apparatus, and a computer program are provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for the calibration patterns. However, there are different procedures and requirements for transmission and reception calibrations. Hence, to reduce the amount of hardware needed to perform transmission and reception calibrations, the data buffers employ additional front end circuitry to reuse the buffers for both tasks.

    摘要翻译： 提供了一种方法，装置和计算机程序来重用功能数据缓冲器。 使用极限数据速率（XDR（TMDR））动态随机存取存储器（DRAM），采用测试模式来动态校准数据与时钟。 为了执行此任务，采用数据缓冲器来存储校准模式的数据和命令。 然而，发送和接收校准有不同的程序和要求。 因此，为了减少执行发送和接收校准所需的硬件数量，数据缓冲器使用附加的前端电路来为这两个任务重新使用缓冲器。

    Method and apparatus for generating a mask value and command for extreme data rate memories utilizing error correction codes
    10.
    发明授权
    Method and apparatus for generating a mask value and command for extreme data rate memories utilizing error correction codes 有权
    用于利用纠错码生成用于极端数据速率存储器的掩码值和命令的方法和装置

    公开(公告)号：US07287103B2

    公开(公告)日：2007-10-23

    申请号：US11130911

    申请日：2005-05-17

    申请人： Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Charles Ray Johns ,  Peichun Peter Liu

    发明人： Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Charles Ray Johns ,  Peichun Peter Liu

    IPC分类号： G06F3/00 ,  G06F12/00

    CPC分类号： G11C7/1006

    摘要： A method, an apparatus, and a computer program product are provided for the handling of write mask operations in an XDR™ DRAM memory system. This invention eliminates the need for a two-port array because the mask generation is done as the data is received. Less logic is needed for the mask calculation because only 144 of the 256 possible byte values are decoded. The mask value is generated and stored in a mask array. Independently, the write data is stored in a write buffer. The mask value is utilized to generate a write mask command. Once the write mask command is issued, the write data and the mask value are transmitted to a multiplexer. The multiplexer masks the write data using the mask value, so that the masked data can be stored in the XDR DRAMS.

    摘要翻译： 提供了一种方法，装置和计算机程序产品，用于处理XDR（TM）DRAM存储器系统中的写掩码操作。 本发明消除了对双端口阵列的需要，因为在接收到数据时完成了掩码生成。 掩码计算需要较少的逻辑，因为256个可能的字节值中只有144个被解码。 掩码值生成并存储在掩码数组中。 独立地，写入数据被存储在写入缓冲器中。 掩码值用于生成写掩码命令。 一旦写掩码命令被发出，写入数据和掩码值被发送到多路复用器。 多路器使用掩码值对写入数据进行掩码，以便将掩蔽的数据存储在XDR DRAMS中。